Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home CPUs Read-only-memory-with-few-programming-signal-lines

 System and method for providing a fault tolerant computer program runtime support environment
The present invention automatically converts a non-fault tolerant software program into a fault-...


 Multiple processor synchronized halt test arrangement
An object of this invention is to provide a stable testing and debugging environment for a ...


 High-availability computer system with a support logic for a warm start
It is an object of this invention to control the assignment of the logic processors to operating ...


 Redundant read bus for correcting defective columns in a cache memory
Generally, the present invention relates to efficiently implementing column redundancy in a cache ...


 Plural sensor monitoring and display device
We claim: 1. In a monitoring device for monitoring the outputs of a plurality of sensors and ...


 Fault diagnostic distributed processing method and system
It is an object of the present invention to provide a distributed processing system which resolves ...


 Method and system for identification of software application faults
What is claimed is: 1. A method for identification of a fault in a software application associated ...


 System for reading system log
The inventive remote access system provides system administrators with new levels of client/server ...


 Shift register programming for a programmable logic device
The present invention describes a novel architecture to improve the performance of a programmable ...


 Complementary logic input parallel (CLIP) logic circuit family
It is therefore an object of the present invention to provide a high speed complementary all-...


 Read-only memory with few programming signal lines

Details
Inventors: Matsubara, Hiroaki;
Assignee: Oki Electric Industry Co., Ltd. (Tokyo, JP)
Primary Examiner: Sikes; William L.
Assistant Examiner: Cunningham; Terry D.
Attorney, Agent or Firm: Manzo; Edward D.

A signal-generating circuit receives a program signal and generates an output enable signal, a control signal, and a latch signal. In response to the output enable signal, a programmable read-only memory outputs data onto a data bus. In response to the control signal, a three-state buffer outputs data from a first register to the data bus; the data can then be stored in the programmable read-only memory by input of a chip enable signal. In response to the latch signal, a second register latches data output from the programmable read-only memory onto the data bus. An equality checker compares the contents of the first and second registers and generates an equal signal indicating whether they are equal.

DETAILED DESCRIPTION It is accordingly an object of the present invention to enable a PROM to be programmed using only a small number of input signals.
A programmable read-only memory circuit has a programmable read-only memory and a signal-generating circuit.
The signal-generating circuit receives a program signal and activates, in sequence, a control signal, an output enable signal, and a latch signal.
A first register receives and holds data to be stored in the programmable read-only memory.
Responsive to the control signal, a three-state buffer outputs data held in the first register onto a data bus.
The programmable read-only memory receives a chip enable signal which causes it to store data from the data bus.
Responsive to the output enable signal, the programmable read-only memory outputs stored data onto the data bus.
Responsive to the latch signal, a second register receives and holds data present on the data bus.
An equality checker compares the contents of the first and second registers and generates an equal signal indicating whether the two contents are equal.



Related patents
  System for dynamically exchanging and matching revision information between host and terminal
An object of the present invention is to eliminate such a drawback and to provide a system for dynamically exchanging the revision information between the host and the ...
  Registered logic macrocell with product term allocation and adjacent product term stealing
This invention provides a macrocell with product term allocation and adjacent product term stealing. Programmable configuration switches provide product term allocation ...
  Apparatus and method for product term allocation in programmable logic
A programmable logic device having an allocation scheme for pooling product terms is described. In the following description, for purposes of explanation, numerous ...
  Level converter circuit for converting ECL-level input signals
It is therefore an object of the present invention to provide a level converter circuit in view of the aforementioned defects of the prior art, which is capable of ...
  Logic gates with controllable time delay
These needs are met by providing a variable threshold voltage logic element. The threshold voltage is controllably varied, using multiplication means, summation means ...
  Programmable logic cell and array
OF DRAWING FIG. 1 depicts an array 10 of cells 20 formed in accordance with the present invention. As is apparent, the cells are arranged in a two dimensional matrix ...
  Output logic macrocell with enhanced functional capabilities
This invention provides an output logic macrocell for use with a logic block such as a programmable logic array. The output logic macrocell contains an XOR gate, an OR ...
  Graphics system including an output buffer circuit with controlled Miller effect capacitance
Generally, and in one form of the invention, an integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage ...
  Safestore frame implementation in a central processor
What is claimed is: 1. In a central processor including: A) data manipulation means for performing successive data manipulation operations and for making safestore ...
  Refresh control for dynamic memory in multiple processor system
In accordance with one embodiment of the invention, a computer system employs three identical CPUs typically executing the same instruction stream, and has two identical,...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved