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Reducing the number of carry-look-ahead adder stages in high-speed arithmetic units, structure and method
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Inventors: Rarick, Leonard D.;
Assignee: Hyundai Electronics America (Milpitas, CA)
Primary Examiner: Malzahn; David H.
Assistant Examiner:
Attorney, Agent or Firm: Townsend and Townsend Khourie and Crew
A carry-look-ahead adder for adding an addend and an augend and generating a final sum. The addend, augend, and final sum are binary numbers, each having a plurality of bits. Bits of the same order in the addend and the augend are organized into columns. The adder has at least one data reduction stage, each data reduction stage having at least one multi-column full adder. The data reduction stages use the columns of addend and augend bits to generate a reduced addend and a reduced augend, with the reduced augend having fewer bits than the augend. A generate/propagate calculation stage then uses the reduced addend and the reduced augend for calculating generate and propagate data, the generate/propagate calculation stage having been modified to account for the reduction of the addend and augend. A carry-generate stage then uses the generate and propagate data to generate at least one final carry. Finally, a final sum calculation stage uses the reduced addend, the reduced augend, and the final carries for calculating the final sum. The data reduction stages reduce the inputs to the generate/propagate calculation stage thereby reducing the number of inputs to the carry-generate circuit. With fewer inputs, the number of stages in the carry-generate circuit can be reduced, thus resulting in a faster implementation of the carry-look-ahead adder. |
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DETAILED DESCRIPTION According to the invention, an add circuit for adding an addend and an augend and generating a final sum is described.
The addend, augend, and final sum are binary numbers, each having a plurality of bits.
Bits of the same order in the addend and the augend are organized into 2-bit columns.
The add circuit comprises at least one data reduction stage, each data reduction stage comprising at least one multi-column full adder.
The data reduction stages use the columns of addend and augend bits to generate a reduced addend and a reduced augend, with the reduced augend having fewer bits than the original augend.
A generate/propagate calculation stage then uses the reduced addend and the reduced augend for calculating generate and propagate data, the generate/propagate calculation stage having been modified to account for the reduction of the addend and augend.
A carry-generate stage then uses the generate and propagate data to generate at least one final carry.
Finally, a final sum calculation stage uses the reduced addend, the reduced augend, and the final carries for calculating the final sum.
The data reduction stages reduce the inputs to the generate/propagate calculation stage thereby reducing the number of inputs to the carry-generate circuit.
With fewer inputs, the number of stages in the carry-generate circuit can be reduced, thus resulting in a faster implementation of the carry-look-ahead adder.
An additional embodiment exists wherein the data reduction stages operate only on specified groups of consecutive columns of addend and augend bits.
These are usually the columns which are at either end of the array of columns generated by a carry-save adder in a binary multiplier.
Because column data toward the ends of the array arrive earlier than column data toward the center of the array, reducing operations are performed only on the earlier arriving columns.
In another embodiment for use in a rounding circuit, the generate/propagate calculation stage is modified to produce a generate and a propagate for a group of consecutive columns where the augend bit for each of the consecutive columns is known to be logic zero
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