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Redundant read bus for correcting defective columns in a cache memory
| Details |
Inventors: Gabillard, Bertrand; Girard, Philippe; Omet, Dominique;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Nguyen; Hoa T.
Assistant Examiner:
Attorney, Agent or Firm: Lau; Richard, Schnurmann; H. Daniel
A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main read bus. Normal and redundant data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers. When the late select address signals become valid, then the correct information can be selected via a multiplexer provided with an INHIBIT input. The multiplexer is normally controlled by decoded signals generated by a decoder, unless redundancy is required. If redundancy is required, the information generated by the bit address comparator forces the multiplexer, via the INHIBIT input, to select the redundant read bus, instead of one read bus of the main read bus, and to output the redundant byte as the selected one. |
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DETAILED DESCRIPTION Generally, the present invention relates to efficiently implementing column redundancy in a cache memory architecture to reach high speed performance.
The invention basically involves the use of a separate redundant read bus fully dedicated to redundancy, fed by a single spare sub-array which is common to all the memory sub-arrays of the cache memory.
As a result, the redundant sense amplifiers are no longer dotted with the normal sense amplifiers on a common read bus.
The redundant sense amplifiers are dotted to the redundant read bus and the normal sense amplifiers are connected to a main read bus comprised of 4 read busses in the case of a 4-way set associative cache memory organization.
Consequently, both the normal and redundant 32 data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers, i.
e.
, on the main and redundant read busses respectively.
When the two late select address signals LS0 and LS1 become valid, then the correct information, i.
e.
the correct 8 data among the 32 to be output, can be immediately selected via a 1/4 multiplexer provided with an INHIBIT (INH) input.
The multiplexer is normally controlled by the four decoded signals (derived from the two late select address signals) generated by a decoder, unless redundancy is required.
In this case, the information generated by the bit address comparator and stored in a latch, combined with the information generated by a late select address comparator, forces the multiplexer via the INHIBIT input, to select the redundant read bus instead of one read bus of the main read bus, to output the redundant byte as the selected one.
With this implementation, the number of redundant cell columns do not increase with the number of late select address signals that are used.
It is preferable to use a very high speed late select address comparator circuit to improve the overall access time, because this circuit intervenes in the critical path of the cache memory architecture and because the final fetch decision is done later in the cycle
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CPUs 
