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| CMOS output buffer circuit with improved ground bounce |
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| Selectable edge rate CMOS output buffer circuit |
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Refresh control for dynamic memory in multiple processor system
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Inventors: Peet, Jr., Charles E.; Allison, John D.; Debacker, Kenneth C.; Horst, Robert W.;
Assignee: Tandem Computers Incorporated (Cupertino, CA)
Primary Examiner: Eng; David Y.
Assistant Examiner:
Attorney, Agent or Firm: Smith; A. C.
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. Each CPU has a local memory, separate from the memory modules, and this local memory is of the dynamic type so it must be periodically refreshed. The refresh cycles are interposed at the same point in the instruction stream for each of the three CPUs by counting instruction execution cycles separately in each CPU, and interrupting to do a refresh cycle when a given count is reached. Stall cycles are also counted, and when long periods of stalls occur then more than one refresh cycle is interposed to catch up to the needed refresh schedule. |
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DETAILED DESCRIPTION In accordance with one embodiment of the invention, a computer system employs three identical CPUs typically executing the same instruction stream, and has two identical, self-checking memory modules storing duplicates of the same data.
A configuration of three CPUs and two memories is therefore employed, rather than three CPUs and three memories as in the classic TMR systems.
Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules.
In order to avoid imposing the performance burden of fault-tolerant operation on the CPUs themselves, and imposing the expense, complexity and timing problems of fault-tolerant clocking, the three CPUs each have their own separate and independent clocks, but are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; the interrupts are also synchronized to the CPUs ensuring that the CPUs execute the interrupt at the same point in their instruction stream.
The three asynchronous memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules at the time of the memory request, but read data is not voted when returned to the CPUs.
The two memories both perform all write requests received from either the CPUs or the I/O busses, so that both are kept up-to-date, but only one memory module presents read data back to the CPUs or I/Os in response to read requests; the one memory module producing read data is designated the "primary" and the other is the back-up.
Accordingly, incoming data is from only one source and is not voted.
The memory requests to the two memory modules are implemented while the voting is still going on, so the read data is available to the CPUs a short delay after the last one of the CPUs makes the request.
Even write cycles can be substantially overlapped because DRAMs used for these memory modules use a large part of the write access to merely read and refresh, then if not strobed for the last part of the write cycle the read is non-destructive; therefore, a write cycle begins as soon as the first CPU makes a request, but does not complete until the last request has been received and voted good
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CPUs 
