Registered logic macrocell with product term allocation and adjacent product term stealing

DETAILED DESCRIPTION This invention provides a macrocell with product term allocation and adjacent product term stealing.
Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register.
Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell.
By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms input to the OR gate of the first macrocell for use in its own OR gate.
An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells.
By the process of adjacent product term stealing, product terms are allocated between macrocells.
Because the programmable configuration switches can direct individual input product terms to the secondary inputs to the register instead of the OR gate, the register and register accompanying logic can be used even when an adjacent macrocell steals the OR gate.
The register and register accompanying logic provide output control for the macrocell.
In one preferred embodiment, an EXCLUSIVE-OR gate with a plurality of selectable inputs allows the register to be implemented as a D or a T flip-flop.