Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home CPUs Router-device-and-data-communication-system-capable-of-suppressing-traffic-increase-in-communications-among-a-plurality-of-lan-segments

 Low power clocking apparatus and method
A low power clocking apparatus and method is used to reduce power consumption by an electronic ...


 On chip monitor
Having thus described our invention, what we claim as new, and desire to secure by Letters Patent ...


 Parallel data transmission unit using byte error correcting code
An object of the invention, therefore, is to overcome the problems existing in the prior art and to ...


 Semiconductor memory device with redundancy structure suppressing power consumption
OF THE PRESENT INVENTION Referring to FIG. 2, the difference between the structure of FIGS. 1 and 2...


 Control circuit and method for controlling a data line switching circuit in a semiconductor memory device
Accordingly, it is an object of the present invention to provide a semiconductor memory device ...


 Scan path circuitry including a programmable delay circuit
In one embodiment, the present invention concerns a circuit for delaying a signal. The circuit ...


 Apparatus and method for enhancing data transfer to or from a SDRAM system
The problems outlined above are in large part solved by an improved memory bus transfer technique ...


 Single-chip microcomputer
The present invention relates to construction of a logic device (a random logic circuit), within ...


 Self-timed interface for a network of computer processors interconnected in parallel
An object of this invention is the provision of a cost effective bus data transfer system that can ...


 Semiconductor integrated circuits with power reduction mechanism
The present invention relates to semiconductor integrated circuits suitable for high-speed and low-...


 Router device and data communication system capable of suppressing traffic increase in communications among a plurality of lan segments

Details
Inventors: Saito, Shuichi;
Assignee: NEC Corporation (Tokyo, JP)
Primary Examiner: Harrell; Robert B.
Assistant Examiner: Maung; Zarni
Attorney, Agent or Firm: Foley & Lardner

In a router device of the present invention, the routing controller refers to the routing address table to determine whether the received frame is to be routed (whether the frame passes through two or more router devices, for example). The multiplication controller multiplies the frame selected as the subject of routing and has the path controller set paths between router devices for transmission of the multiplied frames. The frame for which a path is set is transmitted with the destination address of the router device as the other party of communication. When a multiplied frame is received, the multiplication controller extracts an ordinary frame from the multiplied frame and sends it to the device indicated by the original destination address.

DETAILED DESCRIPTION An object of the present invention is to provide a router device and a data communication system which, in communications among a plurality of LAN segments in connection, suppress traffic increase at the LAN segment as a relay by controlling the data transmission amount corresponding to the traffic amount at this relaying LAN segment and thereby prevent lowering of efficiency of the entire network due to a bottleneck condition at the relaying LAN segment.
Another object of the present invention is to provide a router device and a data communication system which solve the problems of data delay and data transmission incapability due to congestion at the LAN segment as a relay in data sending/receiving among information processors connected to the relaying LAN segment.
According to an embodiment of the present invention to attain the above objects, a router device connected between different LAN segments for mutual communications between them comprises a data sending/receiving control means which receives data signals on the LAN segment and sends data signal to the LAN segment, a link address detection means which selects the data signals treated as the subject of receiving from the data signals received at the data sending/receiving control means, a routing control means which selects the data signals treated as the subject of routing from the data signals selected by the link address detection means, a multiplication control means which multiplies the data signals selected by the routing control means, a path control means which sets paths for the data signals multiplied by the multiplication control means and issues request for data signal sending and a link address setting means which, based on the sending request from the path control means, sets the destination address to the multiplied data signal to send it to the data sending/receiving control means.
According to a further preferred embodiment, a router device further comprises an address table where destination addresses and originating addresses of the data signals to be received are registered in advance and the link address detection means selects the data signals treated as the subject of receiving from the received data signals with reference to the address table



Related patents
  Bus adapter module with improved error recovery in a multibus computer system
It is an object of the present invention to provide a method and apparatus for error recovery in a multibus computer system that maintains system integrity while ...
  Error correction circuit
An error correction circuit of a first aspect of the invention comprises (a) a data buffer for storing a data stream in which a plurality of RS codes for correcting: an ...
  Virtual machine data processor
Accordingly, it is an object of the present invention to provide a data processor which can support a virtual machine environment wherein a faulted instruction may be ...
  Distributed processing system with checkpoint restart facilities wherein checkpoint data is updated only if all processors were able to collect new checkpoint data
It is therefore an object of the present invention to provide a distributed processing system with checkpoint restart facilities which allows each of a number of data ...
  Management method for a multiprocessor system
It is an object of the present invention to solve the above problems. The present invention provides a multiprocessor system including at least one supervisor to which a ...
  CMOS output buffer circuit with improved ground bounce
Accordingly, it is a general object of the present invention to provide a CMOS output buffer circuit with a significant reduction in ground bounce which is relatively ...
  Selectable edge rate CMOS output buffer circuit
I claim: 1. A CMOS tristate output buffer circuit having an output pullup driver (P1) and an output pulldown driver (N1) coupled to an output (V.sub.OUT), a pullup ...
  State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections
The above and other objects of the present invention are achieved in a preferred embodiment of a unit which includes a state machine for defining sequential states used ...
  Software controlled power shutdown in an integrated circuit
An object of the invention is control of power shutdown within an integrated circuit without the use of dedicated package pins. A feature of the invention is the use of ...
  Integrated circuit with a low-power mode and clock amplifier circuit for same
Accordingly, there is provided, in one form, an integrated circuit with a low-power mode, comprising an inverter portion, a resistor, a logic portion, and an internal ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved