Control system having optimality decision means |
| An object of the present invention is to provide a control system having an optimality decision ... |
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Control device for controlling a controlled apparatus, and a control method therefor |
| A--GENERAL PRINCIPLES Referring to FIG. 1, there is shown a control system in which the present ... |
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Decision making method |
| When a human decides the intention to an action, he may decide it imperatively. Actually however, ... |
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Apparatus for page tagging in a computer system |
| It is, therefore, a general object of the present invention to improve and speed the operation of ... |
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Dataprocessing device with instruction cache |
| The invention may be incorporated into a microcomputer which has a peripheral port by which access ... |
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Barrier synchronization for distributed memory massively parallel processing systems |
| To overcome the above described shortcomings in the art and provide key system resources necessary ... |
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Image memory controller for controlling multiple memories and method of operation |
| These and other problems have been solved by us by designing a single memory controller to handle ... |
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Apparatus and method to preserve data in a set associative memory device |
| The invention is an apparatus to dynamically partition a set-associative memory structure. The ... |
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Electronic typewriter with automatic power-off device |
| OF PREFERRED EMBODIMENTS Turning now to FIG. 1, an illustrative electronic typewriter structure is ... |
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Printer interface |
| We claim: 1. A control module for use in a peripheral printer to a host computer, the host computer ... |
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Routing address bit selection in a packet switching network
| Details |
Inventors: Larson, Mikiel L.;
Assignee: AT&T Bell Laboratories (Murray Hill, NJ)
Primary Examiner: Olms; Douglas W.
Assistant Examiner: Scutch, III; Frank M.
Attorney, Agent or Firm: Volejnicek; David
A multi-stage packet switching network (100) includes a plurality of packet switching nodes (110) each included in one stage of a sequence of stages (101, 102, 103) of the network. Each node (101-1-x) of a stage (101) is connected to a stage bus (220-1) that indicates to the node "how manieth" stage in the sequence of stages it is a part of, i.e., where in the sequence of stages that node appears. Each node includes circuitry (450) that responds to the information carried by the associated stage bus to select "that manieth" most significant bit (504) of the destination field (502) of a received packet (500) as the bit on the basis of whose value the packet is routed at the node. On a circuit pack (200) that includes nodes of a plurality of stages, the first stage bus is connected to a register (250) whose contents are the number of the first stage of the pack in the sequence of stages. Adders (210) interconnect the stage buses of sequential stages and act to increment by one the value carried by each sequential stages' stage bus. |
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DETAILED DESCRIPTION Turning now to the drawing, FIG. 1 is a representation of a packet switching network 100 of the type that may be used to configure a packet switching system. In such a system (not shown), trunk controllers interface the network 100 to trunks for communication with other networks and with host interface devices. The network 100 switches packets that it receives over various trunks and that are destined for other trunks and routes the packets on their way through the packet switching system from their source to their destination. The network 100 is illustratively connected to trunk controllers (not shown) by communication links 150. The number of links connecting to a network 100 varies with the size of the network 100 and the number of subtending trunk controllers. While signals may be transmitted over a link in either direction, for purposes of packet transmission the links are unidirectional, in that signal streams that make up packets are transmitted over the links in one direction only. The links 150 may be either bit serial transmission media or bit parallel transmission media. The switching fabric of the network 100 is a matrix of switching nodes 110 that are interconnected by yet other links 150. The interconnection of the nodes 110 is such that groups of nodes 110 form a sequence of n columns, or n stages, of the matrix of the network 100, with each node 110 being a part of one stage. Nodes 110-1-x (x standing for 1, 2, 3, etc. ) of the network 100 are the first in the network 100 to switch packets received over links 150 from trunk controllers, and form a first stage 101 in the sequence of n stages of the network 100; nodes 110-2-x of the network 100 receive packets over links 150 from the nodes 110-1-x of the stage 101, are the second in the network 100 to switch the packets, and form a second stage 102 in the sequence of n stages of the network 100; nodes 110-3-x of the network 100 receive packets over links 150 from the nodes 110-2-x of the stage 102, are the third in the network 100 to switch the packets, and form a third stage 103; and so on
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