Safestore frame implementation in a central processor

DETAILED DESCRIPTION What is claimed is: 1.
In a central processor including: A) data manipulation means for performing successive data manipulation operations and for making safestore information available at the conclusion of each data manipulation operation; B) a result bus coupled to receive safestore information from said data manipulation means; C) a cache data array; D) clock means for generating a multiple phase clock including alternating, non-overlapping .
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1 and .
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2 clock pulse streams; and E) error sensing means for sensing the presence of an error in said central processor and for issuing an error signal indicative thereof; safestore information gathering, storage and delivery means comprising: F) first temporary storage means situated in said cache data array; G) first transfer means for transferring safestore information means available from said result bus into said first temporary storage means upon the occurrence of a first .
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1 pulse; H) second transfer means situated in said cache data array; I) second transfer means for transferring safestore information from said first temporary storage means into said second temporary storage means upon the occurrence of a first .
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2 pulse; J) an XRAM; K) third temporary storage means situated in said XRAM; L) third transfer means for transferring safestore information from said second temporary storage means into said third temporary storage means upon the occurrence of a second .
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1 pulse which is later in time than said first .
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1 pulse; and M) inhibiting means responsive to said error signal to disable said third transfer means; whereby, if an error is sensed, safestore information stored in said third temporary storage means may be accessed for analysis and potential resumption at an operation point immediately preceding that at which an error was sensed.
2.
The central processor of claim 1 which further includes: A) fourth temporary storage means; and B) fourth transfer means for transferring safestore information from said third temporary storage means into said fourth temporary storage means subsequent to disablement by said inhibiting means of said third transfer means