 Data bank priority system |
| OF THE PREFERRED EMBODIMENT Turning now to the drawings, there is shown in FIG. 1 part of a data ... |
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| Integrated circuit device having a memory and majority logic |
| I claim: 1. An integrated circuit device comprising: a memory having at least first, second and ... |
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| Logic circuit system with latch circuits for reliable scan-path testing |
| It is, therefore, a primary object of the present invention to provide an IC logic circuit having ... |
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| Optional single or double clocked latch |
| The present invention is especially directed towards a programmable latching circuit which can ... |
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| Dynamic logic circuit with reduced operating current |
| Accordingly, it is an object of the present invention to provide a dynamic logic circuit which has ... |
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| Edge sensitive set-reset flip flop |
| Accordingly, it is the object of this invention to provide an improved edge sensitive set-reset ... |
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| Master-slave multivibrator with improved metastable response characteristic |
| In accordance with the present invention, a master-slave flip-flop device having a master segment ... |
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| Arbiter circuits with metastable free outputs |
| The two-input arbiter circuit shown in FIG. 1 includes input terminals 10 and 11 and output ... |
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Scalable multiple level tab oriented interconnect architecture
| Details |
Inventors: Ting, Benjamin S.; Pani, Peter M.;
Assignee: BTR, Inc, (Reno, NV)
Primary Examiner: Bowler; Alyssa H.
Assistant Examiner: Nguyen; Dzung C.
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman LLP
A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit This floor plan is a scalable block architecture in which each block connector tab networks of a 2.times.2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4.times.4 block grouping to be scalable. The innovative floor plan makes efficient use of die space with little layout dead space as the floor plan provides for a plurality of contiguous memory and passgate arrays (which provide the functionality of the bidirectional switches) with small regions of logic for CFGs and drivers of the block connector tab networks. Therefore, the gaps typically incurred due to a mixture of memory and logic are avoided. Intra-cluster routing lines and bi-directional routing lines are overlayed on different layers of the chip together with memory and passgate arrays to provide connections to higher level routing lines and connections between CFGs in the block. |
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DETAILED DESCRIPTION An improved field programmable gate array (FPGA) is provided which includes tab network connectors for interfacing groups of logic cells with lower levels of interconnect and for interfacing lower levels of interconnect with higher levels of interconnect.
In one embodiment, the connector is used to interface a group of elements or configurable function generators (CFGs), including storage elements, to certain levels of a hierarchical routing network.
Each group or cluster of a logic block is formed of multiple CFGs programmably coupled to a set of bidirectional input/output lines.
In the present embodiment an innovative cluster architecture is utilized which provides fine granularity without a significant increase in logic elements.
The bidirectional input/output line is coupled to the connector.
The connector includes a connector tab line coupled to the bidirectional input/output line through a programmable switch.
The connector tab line is also coupled to the connector and bidirectional input/output line of an adjacent block.
Frequently, signal routings occur between adjacent blocks, and in the prior art valuable routing lines which interconnect to higher levels of the routing hierarchy were used.
In the improved FPGA of the present invention, a signal from a logic block can be directly routed to an adjacent logic block without utilizing the network of routing lines.
This frees up the valuable routing lines to perform longer, non-adjacent block routings, and therefore the space required for non adjacent routing can be optimized.
An additional, significant advantage is the minimizing of blockage caused by signal routings as each bidirectional input/output line is selectively coupled through two block connector tab networks to the routing hierarchy.
Also coupled to the bidirectional input/output line is a plurality of bidirectional switches that are programmable to permit a signal originating from the bidirectional input/output line to couple to one or more of a plurality of levels of hierarchical routing lines
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CPUs 
