Scan path circuitry including a programmable delay circuit

DETAILED DESCRIPTION In one embodiment, the present invention concerns a circuit for delaying a signal.
The circuit includes a scan register, a logic circuit, and a programmable delay circuit.
The scan register stores scan data and the logic circuit selectively decodes the scan data.
The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.