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| Waste water purifying procedure |
| I claim: 1. A waste water purifying process for treatment of waste water containing chlorinated ... |
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| Methane production by attached film |
| The method for producing methane gas by the present invention is suitable for the treatment of any ... |
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| Chemical detoxification of sewage sludge |
| As shown in FIG. 1, suitable apparatus for practicing the method of the instant invention includes ... |
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| Process for the biological treatment of waste water |
| OF THE INVENTION The process according to the present invention can be implemented to particular ... |
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| Microbial compositions and methods for treating soil |
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| Bioreactor for biological treatment of contaminated water |
| We claim: 1. A bioreactor unit for the aerobic biological treatment of hydrocarbon contaminated ... |
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| Method and apparatus for enhancing filter bed performance |
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| Instantaneously emptiable externally mounted animal food tray |
| I claim: 1. A readily emptiable animal food tray, for use in conjunction with a plurality of animal ... |
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| Secondary sewage treatment system |
| A primary object of the present invention is to provide a secondary sewage treatment system ... |
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Self-diagnostic system for semiconductor memory
| Details |
Inventors: Akiyama, Tsutomu;
Assignee: Ando Electric Co., Ltd. (Tokyo, JP)
Primary Examiner: Beausoliel, Jr.; Robert W.
Assistant Examiner: Chung; Phung M.
Attorney, Agent or Firm: Seidel, Gonda, Lavorgna & Monaco
A self-diagnostic memory checking system includes a data generator for generating and applying data to a selected address of a memory when a CPU is in a memory write mode and generating expected data when the CPU is in a memory read mode. An address generator provides a memory address for the memory. The data is read out of the memory during the memory read mode and is compared to the expected data for detecting errors in the memory. In order to allow memory checking to proceed without constant action by software in the CPU, a range of memory addresses to be tested are loaded into a test finish detector. A separate clock generator provides enabling timing clock pulses to the address generator, data generator and memory in response to a test start signal from the CPU. A switch circuit connects data from the data generator to a first output connected to the data input of the memory when the CPU is in the memory write mode and to a second output when the CPU is the memory read mode. A comparator connected to the output of the memory for comparing the data read from the memory and to the expected data from the second output of the switch circuit gives an output representative of whether the expected data and the data read from the memory are in coincidence. A flip-flop receives the output of the comparator and indicates the result of the comparison. |
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DETAILED DESCRIPTION The present invention aims at providing a self-diagnostic system for memory which comprises, in addition to the parts of the conventional system shown in FIG.
6, a clock generator, test finish detector, S.
W.
circuit, and flip-flop (hereinafter called "FF"), so that the diagnosis can be controlled by the hardware to shorten the diagnosis time.
To achieve the above aim, the system according to the invention comprises a CPU 1 in which a sequence program for diagnosis is written; a data generator 2 which generates data to be applied to a memory 5 when the CPU 1 is in the memory write mode and generates expected data when the CPU is in the memory read mode; an address generator 3 which gives an address to be written in the memory 5 to the address input of the memory when the CPU 1 is in the memory write mode and transfers an address read out from the memory 5 to the address input of the memory when the CPU is in the memory read mode; a clock generator 6 which is started with a test start signal 1c from the CPU 1; a test finish detector 7 which is operated with the output clock of the clock generator 6, detects the finish of a test with the address generator 3 that generates an address, and stops the operation of the clock generator 6; an S.
W.
circuit 8 which receives the output from the data generator 2 and, under the command of the CPU 1, transmits the data as the first output 8a to the data input of the memory 5, takes up expected data from the CPU 1 into the data generator 2, and changes the expected data to be the second output 8b; a comparator 4 which receives data read from the memory 5 as the first input and the second output 8b from the S.
W.
circuit 8 as the second input, compares the output data from the memory 5 with the expected data, detects whether the expected data and the output data from the memory 5 are in coincidence or not, and decides that the memory 5 is sound or erroneous; and an FF 9 which takes the output from the comparator 4 as a set signal and the test start signal 1c from the CPU 1 as a reset signal
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CPUs 
