Self-timed data pipeline apparatus using asynchronous stages having toggle flip-flops

DETAILED DESCRIPTION The present invention finds application in the area of asynchronous circuits, and more particularly, in the area of self-timed data pipelines.
The present invention can be utilized in any context where data is pipelined including, for example, in a network interface controller within a parallel processing system.
In accordance with the present invention, a self-timed data pipeline is comprised of a plurality of pipeline stages.
Each of these pipeline stages comprises at least one data latch coupled to selectively configured combinational logic.
The combinational logic is selectively configured to suit the demands of the particular data pipeline and provides clocking to the at least one data latch in the pipeline stage.
The pipeline stages can advantageously communicate with one another, and pass data in an asynchronous fashion through the use of READY and ACKNOWLEDGE signals.
In a first embodiment, described herein, the combinational logic within a pipeline stage incorporates a first logical AND gate, a second logical AND gate, a logical OR gate, a driver, and a Toggle flip-flop.
In this embodiment, a READY signal from a prior pipeline stage is coupled as a first input to the first logical AND gate, and is inverted, and coupled as a first input to the second logical AND gate.
An ACKNOWLEDGE signal from a subsequent pipeline stage is coupled as a second input to the second logical AND gate, and is inverted, and coupled as a second input to the first logical AND gate.
The Q output of the Toggle flip-flop is coupled as a third input to the first logical AND gate, and is inverted, and coupled as a third input to the second logical AND gate.
The outputs of the first and second logical AND gates are then coupled to the input of the logical OR gate.
The driver then drives the output of the logical OR gate to the clock inputs of the data flip-flops in the pipeline stage.
The Q output of the Toggle flip-flop is coupled to the D input of toggle flip-flop, while the Q output of Toggle flip-flop outputs the READY signal and the ACKNOWLEDGE signal for this particular pipeline stage