 Apparatus and method for positioning an integrated circuit chip within a multichip module |
| OF THE INVENTION This description is divided into three sections. The first is a description of ... |
|
| Surface profile and material mapper using a driver to displace the sample in X-Y-Z directions |
| The present invention provides a versatile and high resolution microscopy technique that uses a ... |
|
| Method and apparatus for manufacturing known good semiconductor die |
| In accordance with the present invention, a method and apparatus for manufacturing known good die ... |
|
| Extraneous substance inspection method and apparatus |
| An object of the present invention is to provide an extraneous substance inspection method in which ... |
|
| Deep trench etch on bonded silicon wafer |
| A sequence of steps for carrying out the invention is shown in FIGS. 2A-2D where like reference ... |
|
| Integrated circuit fabrication critical dimension control using self-limiting resist etch |
| In a basic aspect, the present invention provides an integrated circuit fabrication critical ... |
|
| Boot drive selection and hibernation file detection |
| The present invention allows the portable computer to boot from a predetermined list of bootable ... |
|
| Use of a cache ownership mechanism to synchronize multiple dayclocks |
| The present invention overcomes the problems found in the prior art by providing a method of and ... |
|
| Integrated services digital network based facility management system |
| The present invention provides for a facility management system with at least four facility control ... |
|
|
Semiconductor device and power converter using same
| Details |
Inventors: Mori, Mutsuhiro; Yasuda, Yasumichi; Hosoya, Hiromi;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Mintel; William
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP.
A high voltage semiconductor device is provided with a p layer which forms a main pn- junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n+ layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers and reaching the surface of an n- layer through an insulating film, the area of the field plates being not less than one half of the n- surface. This arrangement is effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is vey effective in improving the reliabilty of a high voltage control unit. |
|
DETAILED DESCRIPTION The semiconductor device according to the present invention has a pair of main surfaces.
On one main surface side, the surface of a first semiconductor region of a first conduction type is in contact with the main surface, and there is formed a second semiconductor region of a second conduction type extending into the first semiconductor region.
Further, in a surrounding relation to the second semiconductor region there is formed a third semiconductor region of a second conduction type extending into the first semiconductor region.
On the other main surface side of the semiconductor device, there is formed a first main electrode, and in the second semiconductor region is provided a second main electrode which is in ohmic-contact with the second semiconductor region and which covers the surface of the first semiconductor region through an insulating film.
Further, in the third semiconductor region is provided an auxiliary electrode which is in contact at a low resistance with the third semiconductor region and which covers the surface of the first semiconductor region through an insulating film on the second semiconductor region side and on the side opposite thereto.
In such a structure, at the surface of the first semiconductor region which is in contact with one main surface of the semiconductor device, the area of the region covered with the auxiliary electrode is set at a value not less than one half of the area of the surface of the first semiconductor region which is in contact with one main surface.
In the present invention, when the junction of the first and second semiconductor regions is reverse-biased, the equipotential lines spread over the main surfaces of the semiconductor device are once gathered in the electrode-uncovered region of the first semiconductor region surface and are again spread in the first semiconductor region.
In this case, since one half or more of the surface of the first semiconductor region which is in contact with one main surface of the semiconductor device is covered with the auxiliary electrode, i
|
|
CPUs 
