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Home CPUs Semiconductor-integrated-circuit-device-having-a-hierarchical-power-source-configuration

 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST*** *** NO IMAGES AVAILABLE***
Description:...


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Details
Inventors: Ooishi, Tsukasa;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Nguyen; Viet Q.
Assistant Examiner:
Attorney, Agent or Firm: Lowe, Price, LeBlanc & Becker

A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor. A semiconductor memory device can be realized which reduces the sub-threshold current that flows upon standby of the gate circuit and minimizes a difference in voltage between the sub source voltage transmission line and the main source voltage transmission line to operate at high speed with low current consumption.

DETAILED DESCRIPTION It is therefore an object of the present invention to provide a semiconductor integrated circuit device which can be operated stably and at high speed with low current consumption even in the case of a low power source voltage.
It is another object of the present invention to provide a semiconductor integrated circuit device having a power source arrangement that is able to sufficiently suppress a sub-threshold current which flows through an MOS transistor.
It is a further object of the present invention to provide an internal voltage generating circuit capable of stably generating a high voltage and a negative voltage even in the case of a low power source voltage.
It is a still another object of the present invention to provide a semiconductor integrated circuit device having a source arrangement which reduces a load on the internal voltage generating circuit.
It is a yet another object of the present invention to provide a semiconductor integrated circuit device having a power source arrangement capable of sufficiently controlling a sub-threshold current even when a logic level of an input signal during a standby cycle cannot be predicted.
It is a still further object of the present invention to provide a semiconductor integrated circuit device capable of easily realizing a power source arrangement for suppressing a sub-threshold current.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device including a main voltage transmission line for transmitting a voltage of a first logic level, a sub voltage transmission line, a resistive element connected between the main voltage transmission line and the sub voltage transmission line, a capacitor connected between the sub voltage transmission line and a node for supplying a voltage of a second logic level and composed of an insulated gate type field effect transistor, and a gate circuit operating with a voltage on the sub voltage transmission line as one operating source voltage to perform a predetermined logic process on a received signal and output the processed signal therefrom



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