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Semiconductor-memory-device-comprising-address-holding-flip-flop

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Semiconductor memory device comprising address holding flip-flop

Details

Inventors: Ooami, Kazuo; Sugo, Yasuhisa;
Assignee: Fujitsu Limited (Kawasaki, JP)
Primary Examiner: Moffitt; James W.
Assistant Examiner:
Attorney, Agent or Firm: Staas & Halsey

This invention relates to a semiconductor memory having flip-flops which hold the address input in order to absorb skew thereof within the same chip. The flip-flops are connected to be of the master-slave type and an address decoder is provided between the master flip-flops and the slave flip-flops. A part of the time required for latching the address signal into the master flip-flops and a part of the time required for decoder operation are overlapped, and thereby a high operation rate can be realized. Parts of the circuits forming the flip-flop circuits are used in common to the address input buffer and also in common to the word line driver circuits.

DETAILED DESCRIPTION This invention is intended to solve the above problem by providing a semiconductor memory device which comprises said flip-flop within the IC and realizes a higher operation rate by executing decoding in parallel by a decoder while a buffer circuit absorbs a skew in the time of when an address information appears.
In order to attain this object, a semiconductor memory device of this invention is characterized by that a decoder is provided between the master flip-flop and the slave flip-flop.

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