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Shared memory multiprocessor performing cache coherency
| Details |
Inventors: Tarui, Toshiaki; Okazawa, Koichi; Okada, Yasuyuki; Shonai, Toru; Okochi, Toshio; Akashi, Hideya;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Yoo; Do Hyun
Assistant Examiner: Nguyen; T.
Attorney, Agent or Firm: Beall Law Offices
A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is "0", a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed. |
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DETAILED DESCRIPTION In the case of constructing a switch type SMP and further dividing the interior of the SMP into partitions, as stated in the Prior Art, there are three problems to be mentioned below.
(A) Slow Access to Local Main Memory In a case where the processor accesses the main memory included in the same board, ideally it ought to be accessible at high speed without passing through the crossbar switch.
In actuality, however, the transaction for maintaining the cache coherency must be submitted to the other processors so as to check the caches of the other processors (hereinbelow, this processing shall be called the "CCC: Cache Coherent Check").
This is because there is a possibility that the copy of the accessed data has been buffered in the cache of another processor.
In the case where the data has been actually buffered in the cache of any other processor, the CCC is required.
However, in a case where the accessed data is local data having never been accessed from any other processor, there is no possibility that the corresponding data has been buffered in the cache of any other processor, CCC could be omitted.
Therefore, the wasteful CCC incurs, not only the drawback that the access latency is prolonged, but also the drawback that the traffic in the switch is enlarged.
In the directory based protocol, on the other hand, the wasteful CCC does not occur because directory makes it possible to tell which processors have a copy of data line in the cache.
As stated before, however, the directory based protocol has, not only the drawback that the amount of hardware for the directory is large, but also the drawback that overhead for managing the directory is very large.
By way of example, the directory of a system with 16 processors, "4 GB" main memory and "64 B"/line requires a main memory capacity which is as large as: 4 GB/64 B.
times.
16 bits=128 MB Accordingly, a sharp reduction in the amount of hardware is necessitated.
(B) Addresses of Partition not Beginning at Address "0" With the partition management mechanism in the prior art, the whole system forms the unitary address space
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