 Electronic typewriter with automatic power-off device |
| OF PREFERRED EMBODIMENTS Turning now to FIG. 1, an illustrative electronic typewriter structure is ... |
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| Printer interface |
| We claim: 1. A control module for use in a peripheral printer to a host computer, the host computer ... |
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| Engine bearing assembly |
| It is an object of the invention to provide a high temperature dry rolling element bearing assembly.... |
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| Printing system having control language command and raster pixel image data processing capability |
| A host computer includes a processor, a first memory for storing a bit map representation of an ... |
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| Printing system and method |
| In accordance with the illustrative embodiments, demonstrating features and advantages of the ... |
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| Color image forming apparatus |
| The principal object, therefore, of the present invention is to solve the aforementioned problems ... |
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| Display device for use in an electronic balance |
| OF THE INVENTION FIG. 1 illustrates an electronic balance in which a display device embodying the ... |
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| Measuring apparatus with automatic operating mode-setting |
| Accordingly, we claim: 1. Measuring apparatus such as a scale comprising an information generating ... |
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| CMOS RAM data compare circuit |
| Accordingly, it is a general object of the present invention to provide an improved comparator ... |
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| Filtration system for spas, hot tubs, swimming pools and the like |
| Refer now to the drawings and particularly, to FIGS. 1, 2 and 3. Shown in the drawings is a heater ... |
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Single-chip microcomputer having a memory including a one-bit memory element which has 3 inputs and a selector for selecting one of the inputs
| Details |
Inventors: Masumura, Shigeki; Aizawa, Tatsuya; Naito, Kazuo; Miwa, Yoshiyuki; Nakamura, Hideo; Sawase, Terumi; Akao, Yasushi;
Assignee: Hitachi, Ltd. (Tokyo, JP); Hitachi VLSI Engineering Corporation (Tokyo, JP)
Primary Examiner: Black; Thomas G.
Assistant Examiner: Harrity; Paul
Attorney, Agent or Firm: Fay, Sharpe, Beall, Fagan, Minnich & McKee
A single-chip microcomputer includes a microprocessor, a subprocessor for performing peripheral functions, an external port for controlling an input/output operation from/to an external device and a multi-functional logic-in-memory for inputting a plurality of data from at least one of the microprocessor, the subprocessor and the external port and selecting write data from among the plurality of data in accordance with predetermined priorities. |
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DETAILED DESCRIPTION An object of the present invention is to provide a microcomputer in which the above five processing functions can be performed and there is provided a multi-functional logic-in-memory (multi-functional logical buffer memory) for realizing an input/output interface in which some of the above processing functions can be set freely.
In order to attain the above object, the microcomputer according to the first aspect of the present invention includes the logic-in-memory circuit in which a control circuit for performing necessary functions is provided for each storage element and can select a plurality of data from a microprocessor, a subprocessor, an externally connecting port and the like in accordance with predetermined priorities.
In the microcomputer according to the second aspect of the present invention, the storage elements are grouped in accordance with necessary functions so as to properly and distributedly assign respective functions to addresses.
In the microcomputer according to the third aspect of the present invention, the storage elements are integratedly arranged in a matrix manner so that each storage element is selected and controlled in accordance with a combination of a column selecting signal and a row selecting signal.
Furthermore, the multi-functional logic-in-memory is provided to include a control circuit for selecting a plurality of data in accordance with predetermined priorities and its application is not limited to a microcomputer.
According to the present invention, by providing a control circuit as mentioned above, data indicating necessary functions can be set in each storage element independently and thereby the multiple access processing function described in the above (5) can be realized in principle.
In a case that each control circuit is provided for a storage element so that an area for a layout of the control circuits and the storage elements increases, that is, in a case that an area efficiency of a chip is lowered for integration of many storage elements, the structure of the second or third aspect is effective
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