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Home CPUs Split-slave-dual-path-D-flip-flop

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 Split-slave dual-path D flip flop

Details
Inventors: Hill, Anthony M.; Ko, Uming;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Lam; Tuan T.
Assistant Examiner:
Attorney, Agent or Firm: Marshall, Jr.; Robert D., Laws; Gerald E., Donaldson; Richard L.

A D flip-flop circuit has two current paths supply the output signal of this flip-flop. A push-pull circuit including an inverter and a transmission gate clocked in a first phase supplies the output of the D flip-flop in a first output path. A slave latch connected to the transmission gate having an output clocked in a second phase opposite to the first phase serves as the second path to the output. In one alternative embodiment the master latch includes a transmission gate clocked in the second phase serving as input and a pair of cross coupled inverters serving as latch. The master latch may include a feedback P-type MOSFET. The slave latch may includes two slave latch inverters and a transmission gate clocked in the second phase connected to the output of the D flip-flop output. In a second alternative, an appropriately clocked tri-state inverter replaces the second slave latch inverter and the transmission gate. The master latch and the push-pull circuit may be combined and include two inverters, two transmission gates and a feedback P-type MOSFET. In a third embodiment the push-pull circuit consists of an appropriately clocked tri-state inverter.

DETAILED DESCRIPTION This invention is a D flip-flop circuit.
Two independent paths drive the output signal of this flip-flop.
In a first embodiment a push-pull circuit includes an inverter having an input connected to the output of a master latch and a transmission gate clocked in a first phase which supplies the output of the D flip-flop.
This is the first output path.
A slave latch connected to the output of the transmission gate also drives the output during a second phase opposite to the first.
The output of the slave latch serves as the second path to the output of the D flip-flop circuit.
In one alternative embodiment the master latch includes a transmission gate clocked in the second phase serving as input and a pair of cross coupled inverters serving as latch.
The master latch may include a P-type MOSFET in the feedback path.
This feedback P-type MOSFET has its source-drain path connected between the output of a second master latch inverter and the input of a first master latch inverter.
Its gate receives a clock signal in the first phase.
This P-type MOSFET may be replaced by a transmission gate.
There are two alternatives for the slave latch.
In the first alternative, the slave latch includes a first slave latch inverter having an input connected to the output.
A second slave latch inverter has an input connected to the output of the first slave latch inverter.
A transmission gate clocked in the second phase connects the output of the second slave latch and the D flip-flop output.
In a second alternative, an appropriately clocked tri-state inverter replaces the second slave latch inverter and the transmission gate.
In a second embodiment of the invention circuits of the master latch and the push-pull circuit are combined.
As combined these circuits include two inverters and two transmission gates.
An input first transmission gate is clocked in a first phase.
A first master latch inverter has its input connected to the output of the first transmission gate.
A second master latch inverter has its input connected to the output of the first master latch


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