Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home CPUs Static-clock-generator

 Semiconductor integrated circuits with power reduction mechanism
The present invention relates to semiconductor integrated circuits suitable for high-speed and low-...


 Semiconductor integrated circuit device having power reduction mechanism
It is an object of the present invention to provide a semiconductor integrated circuit capable of ...


 Semiconductor integrated circuit device having a hierarchical power source configuration
It is therefore an object of the present invention to provide a semiconductor integrated circuit ...


 Semiconductor integrated circuit device in which influence of power supply noise on internal circuitry during operation of input/output buffer is prevented
An object of the present invention is to provide semiconductor integrated circuit device in which ...


 Refresh method capable of reducing memory cell access time in semiconductor memory device
Therefore, an object of the present invention is to provide a refresh method for a semiconductor ...


 Food pouch with integral collar
In order to overcome the limitation and economic drawbacks encountered in the manufacture of ...


 Apparatus for evaluating a polynomial function using an array of optical modules
I claim: 1. Apparatus for providing an optical analog intensity that is approximately proportional ...


 Method and apparatus for detecting a binary convoluted coded signal
Matched filters for detecting signals of known wave-shape are extensively used in sounding or ...


 Bus control method and apparatus
An object of the present invention is to provide a bus control method and apparatus which, in order ...


 Method of automatically extracting a contrasting object in a digital image
What is claimed is: 1. A method for extracting a contrasting object in a digital image comprising: ...


 Static clock generator

Details
Inventors: McDermott, Mark W.;
Assignee: Cyrix Corporation (Richardson, TX)
Primary Examiner: Butler; Dennis M.
Assistant Examiner:
Attorney, Agent or Firm: Viger; Andrew S., Maxin; John L.

A processing system includes clock circuitry that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated, A cascaded--dual tap delay line is employed having a single phase inversion which is looped back and logically ORed with the first edge of the stimulus signal to induce oscillation. A multiplier/divisor control signal adjusts the "N" times multiplication by disabling the loop after the desired number of pulses is achieved within the period of the stimulus signal. 1/M multiplication is achieved by disabling the loop from oscillating for M stimulus clocks. Multiple frequencies can be dynamically realized on-the-fly without resynchronization by combining delayed clock pulses with a multiplexer.

DETAILED DESCRIPTION To overcome the limitations of the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a computing system and method having a static clock generator that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated.
The stimulus signal is passed through a cascaded--dual tap delay line having a single phase inversion which is looped back and logically ORed with the first edge of the stimulus signal to induce oscillation.
A multiplier/divisor control signal adjusts the "N" times multiplication by disabling the loop after the desired number of pulses is achieved within the period of the stimulus signal.
1/M multiplication is achieved by disabling the loop from oscillating for M stimulus clocks.
Multiple frequencies can be dynamically realized on-the-fly without resynchronization by combining delayed clock pulses with a multiplexer.
It is an object of the present invention therefore, to provide a system and method of statically generating clock signals from a single stimulus edge which can then be removed without impacting oscillation.
It is a further object of the present invention to provide a system and method of statically generating clock signals which can change frequencies on-the-fly without resynchronization and without inducing latency into the system.
These and various other objects, features, and advantages of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof.
However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described a specific example of a distributed clock generator in a computing system, practiced in accordance with the present invention



Related patents
  Integrated circuit binary data output interface for multiplexed output of internal binary information elements from input/output pads
FIG. 1 shows an integrated circuit comprising an interface according to the invention. Conventionally, the circuit 1 shown comprises two pads 2 and 3 to receive a ...
  Field programmable gate array with mask programmable I/O drivers
FIG. 2 is a block diagram of a configurable logic block (CLB) 200 in accordance with one embodiment of the invention. CLB 200 includes programmable interconnect ...
  Flip-flop circuit and electronic device including the flip-flop circuit
It is an object of this invention to provide a flip-flop circuit. The flip-flop circuit includes a dynamic circuit which is operable also in a low-frequency cycle. A ...
  Pulse-to-static conversion latch with a self-timed control circuit
It is therefore an object of the present invention to provide circuit techniques for interfacing dynamic and static circuits via a latch. It is another object of the ...
  Split-slave dual-path D flip flop
This invention is a D flip-flop circuit. Two independent paths drive the output signal of this flip-flop. In a first embodiment a push-pull circuit includes an inverter ...
  Pulse generator
OF THE INVENTION Reference will now be made in detail to the presently preferred embodiments of the invention as illustrated in the accompanying drawings, in which like ...
  Data flow processor which combines packets having same identification and destination and synchronizes loop variables for detecting processing loop termination
An object of the present invention is to provide an execution control system of a data flow program which can eliminate the above described problems and which has a high ...
  Method and apparatus for real time compression and decompression of a digital motion video signal using a fixed Huffman table
A method and apparatus for real time compression and decompression of a digital motion video signal is disclosed. According to the present invention, a bitstream ...
  Method and apparatus for encoding/decoding image data
OF THE PREFERRED EMBODIMENT The present invention relates to a method and apparatus for video encoding/decoding. In the following description, for the purposes of ...
  System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry
The invention provides a computer system including a microprocessor on a single integrated circuit chip comprising an on-chip CPU with a plurality of registers, a ...

0.024

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved