System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry

DETAILED DESCRIPTION The invention provides a computer system including a microprocessor on a single integrated circuit chip comprising an on-chip CPU with a plurality of registers, a communication bus providing a parallel communication path between said CPU and at least one other module with logic circuitry connected to said bus, the on-chip circuitry being operable to receive on said bus digital data packets including control bits and said module being operable to receive the packet and respond thereto independently of operation of the CPU, said integrated circuit device further comprising an external communication port connected to said bus, said port having an internal signal connection to said bus, said internal connection having an internal parallel format, an external signal connection having an external format less parallel than said internal format, and translation circuitry to effect conversion of digital signal packets between said internal and external format, said input port being operable independently of operation of said CPU.
Preferably said translation circuitry is arranged to translate bit packets between an on-chip bit parallel format and an external bit serial format.
Preferably said on-chip CPU includes circuitry for generating bit packets including a destination identifier within each packet, said translation circuitry being operable to translate packets between said internal and external formats while retaining identification of said destination.
Preferably said packets comprise request packets for sending from a packet source to a destination, said source and destination being both connected to said communication bus, and response packets for return from a said destination to said source.
Said single integrated circuit chip may have a plurality of CPUs on the same chip each connected to said communication bus wherein each CPU on said chip may address said external port.
Preferably the or each on-chip CPU has a first memory local to the CPU, and an external computer device is connected to said external communication port, said external computer device having a second memory local to the external computer device