Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home CPUs System-and-method-for-efficient-failover-failback-techniques-for-fault-tolerant-data-storage-system

 Logical view and access to physical storage in modular data and storage management system
OF THE DRAWINGS An exemplary description of the principles according to the present invention may ...


 Method of creating a storage area & storage device
According to conventional techniques, it is necessary for a user to prepare beforehand LUN for the ...


 Method and arrangement for the suppression of rain echos in a terrain following radar
The present invention seeks to solve the problem of developing a process of the kind specified at ...


 Slotted ring shaped antenna
We claim: 1. A vertically polarized antenna conforming to the size requirements of a system ...


 CDMA method with increased capacity
The invention remedies the problem of this limit of messages if the encoding sequences are N bits ...


 Ecological system and method
OF PREFERRED EMBODIMENTS The concept of the present invention will be best understood in ...


 Waste water purifying procedure
I claim: 1. A waste water purifying process for treatment of waste water containing chlorinated ...


 Methane production by attached film
The method for producing methane gas by the present invention is suitable for the treatment of any ...


 Chemical detoxification of sewage sludge
As shown in FIG. 1, suitable apparatus for practicing the method of the instant invention includes ...


 Process for the biological treatment of waste water
OF THE INVENTION The process according to the present invention can be implemented to particular ...


 System and method for efficient failover/failback techniques for fault-tolerant data storage system

Details
Inventors: McKean, Brian D.; Otterness, Noel S.; Skazinski, Joseph G.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Beausoliel; Robert
Assistant Examiner: Wilson; Yolanda L.
Attorney, Agent or Firm: Ananian; R. Michael, Samodovitz; Arthur J.

Structure and method for efficient failover and failback techniques in a data storage system utilizing a dual-active controller configuration for minimizing a delay in responding to I/O requests from a host system following a controller failure is described. A stripe lock data structure is defined to maintain reservation status or stripe locks of cache lines within data extents that are part of a logical unit or storage volume. When a controller fails, dirty cache line data of a failed controller is taken over by a survivor controller. The stripe lock data structure is used to process I/O requests from a host system, by the failed controller. The data storage system functions in a single-active configuration until the dirty cache line data is flushed to one or more storage volumes, by the survivor controller. The inventive structure and method provide utilize a storage volume reservation system. The stripe lock data structure is defined in memory within each of the two or more caching controllers. The stripe lock data structure is used to provide consistent information within each of the two or more caching controllers, and the stripe lock data structure is used by a failed controller to process I/O requests from a host system until dirty cache line data is flushed to one or more storage volumes by a survivor controller. Provides a method and structure which minimizes a delay required to begin processing of host I/O request following a controller failure.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION One technique for overcoming the controller failure problem described in the Background above is a cache mirroring system, apparatus and method for a dual-active controller environment as described in co-pending U.
S.
patent application Ser.
No.
09/410,168 filed Sep.
30, 1999 and entitled System, Apparatus & Method Providing Cache Data Mirroring To A Data Storage System, assigned to the assignee of the present invention and hereby incorporated by reference.
Referring to FIG.
1, a data storage system 100 utilizing a dual-active controller configuration is depicted.
In accordance with the cache data mirror method, a Controller A (primary controller) 116 receives a write data request from the host system 102, the write data request includes data to be written by the primary controller 116 to the storage subsystem.
The primary controller 116 caches the data into the primary controller 116 cache memory 120.
Next, the primary controller 116 mirrors the data to Controller B (alternate controller) 118, such that the alternate controller 118 copies the data into an alternate controller cache memory 122, thereby providing a backup copy of the primary controllers 116 data in case of a controller failure.
Referring to FIG.
2, an exemplary controller 160 is depicted.
The controller 160 includes a CPU 162, a PROM 178, RAM memory 164, and a cache memory 172.
The cache memory 172 includes a read/write (R/W) cache area 174, and a mirror area 176.
The R/W cache area 174 is used as an intermediate storage area for cache line data in order provide the host system 100 optimized access to the cache line data without having to access the storage subsystem 108, 110.
The mirror area 176 is used to store a backup copy of cache line data (backup data) mirrored from a partner controller.
The mirror area 176 is provided to allow a survivor controller to take over the tasks and cache line data of a failed controller.
However, in the event of a controller failure, the survivor controller must perform several task before resuming processing of host I/O requests



Related patents
  Method and system for cache management algorithm selection
Against this backdrop embodiments of the present invention have been developed. Embodiments of the present invention include a system and method of adaptively selecting ...
  Extended definition widescreen television signal processing system with alternate subcarrier
What is claimed is: 1. In a system for processing a television-type signal representative of a widescreen image having a main component and a widescreen component ...
  Apparatus and method for reducing quantizing distortion
This invention is a method and apparatus for passing quantized electronic signals of a given quantizing resolution through processing systems which have a quantizing ...
  Ghost cancelling reference signal transmission/reception system
An object of the present invention is to eliminate group-delay distortion, frequency-amplitude characteristic distortion, ghost and the like from the television signal ...
  Self-diagnostic system for semiconductor memory
The present invention aims at providing a self-diagnostic system for memory which comprises, in addition to the parts of the conventional system shown in FIG. 6, a clock ...
  Image method and apparatus for processing multiple jobs
The present invention aims at eliminating the drawbacks found in the above-mentioned conventional devices. Accordingly, it is an object of the invention to provide an ...
  Method and apparatus for providing system level errors in a large disk array storage system
In accordance with the present invention a storage system is provided which includes at least one host controller that serves as an interface between a host computer and ...
  Method and apparatus for extending commands in a cached disk array
In accordance with the present invention, a storage system is provided which includes a storage controller coupled to a bus and further coupled to a storage device. The ...
  Fibre channel switching fabric
The present invention described and disclosed herein comprises a method and apparatus for transporting Fibre Channel frames between attached devices. The apparatus ...
  Fibre channel controller having both inbound and outbound control units for simultaneously processing both multiple inbound and outbound sequences
The present invention pertains to a FC controller that interfaces between a host system and a 10-bit FC interface. The FC controller has the capacity to act as both a ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved