Test management system to acquire, process and display test data

DETAILED DESCRIPTION The present invention is a test management system for acquiring, processing and displaying test data, the test management system including a data acquisition system comprising a common logic subsystem, a global memory subsystem, a control processor subsystem, a graphics processor subsystem, a communication controller and a disk controller, all coupled to a VME bus, a number of signal conditioners coupled to a data collection system (DSC) bus, and a sequencer and a collect processor coupled to both the DCS bus and the VME bus.
The graphics processor subsystem is coupled to the control processor subsystem via an RS232C port, and receives system clock and system reset signals from the VME bus.
Analog and digital signals are sampled and the voltage and/or frequency values digitized by the signal conditioners at programmed sampling rates.
A data word representative of each sampled digitized value is applied to the sequencer via the DCS bus and is transferred to global memory via the VME bus for storage.
A system master operating system resides in a read only memory of the control processor subsystem.
The control processor subsystem initializes the overall test management system and acts as a system controller and resource manager.
The control processor subsystem handles all internal and certain VME bus interrupts.
An operator inputs test plan information into the data acquisition system through the graphics processor subsystem into the control processor subsystem.
The control processor subsystem translates the test plan information into commands which are given to the other subsystems, typically the collect processor and the disk controller.
The sequencer collects data from the DCS bus according to an address table set up by the collect processor and transfers the data to the global memory subsystem via the VME bus.
The sequencer includes a scan table memory which stores the global memory subsystem addresses of the signal conditioners.
The addresses are stored in the global memory by the control processor subsystem