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 Testing integrated circuits provided on a carrier

Details
Inventors: Sauerwald, Wilhelm A.; De Jong, Franciscus G. M.;
Assignee: U.S. Philips Corporation (New York, NY)
Primary Examiner: Baker; Stephen M.
Assistant Examiner:
Attorney, Agent or Firm: Barschall; Anne E.

A method for testing integrated circuits provided on a carrier. The circuits include a series input (22) and a series output (24) for test and result patterns. A mode control register (30) receives a mode control signal train via the serial input. Under the control of said mode control signal train the serial input and output can be shortcircuited to each other, or further registers (32, 34, 36) can be selectively filled and emptied. In this manner, both the interior of the integrated circuit and respective interconnection functions can easily be tested by a universal protocol. Integrated circuits and the carrier only require minor extension/adaptations.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Description of an integrated circuit.
FIG.
1 is a block diagram of an integrated circuit embodying the principle of the invention.
The envelope is denoted by the block 20.
The circuit comprises four registers 30, 32, 34, 36.
The shift register 30 is fed via switch 42 by input 22 to receive a mode control signal train; in this simple embodiment it accommodates four bits.
The storage thereof is synchronized by clock pulses at terminal CL and is done under the control of a first control signal at terminal TST which indicates that a serial pattern is received and a second control signal at terminal C/D which sets the switch 42 in the top position and thus signals that the mode control signal train can be received.
In the non-test position the registers 32, 34, 36 are transparent and not noticeable to the outside world.
The actual user function of the circuit is fulfilled by the bistable elements of register 34 (in this example also four) and the block 38 which in this case comprises combinational logic not further specified (and optionally further elements).
The bistable elements of register 34 operate by their bidirectional coupling with block 38 as internal flipflops of said block.
In the input/output states register 34 is operated in the usual scan-test manner to communicate a test/result pattern from to the outside world.
In another realization it operates to store information with which internal flipflops can be preset to a relevant value.
In that case the actual function of the integrated circuit is fulfilled entirely by block 38.
The flipflops of register 34 and the flipflops which are set thereby may be situated at any position within the block 38.
For simplicity the user function is not further specified.
It is also possible that the internal scan test is not implemented, but that the output of register 32 is directly connected to the input of register 36.
Register 32 in this example comprises six stages which can be filled in parallel via input 26



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