 Optional single or double clocked latch |
| The present invention is especially directed towards a programmable latching circuit which can ... |
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| Dynamic logic circuit with reduced operating current |
| Accordingly, it is an object of the present invention to provide a dynamic logic circuit which has ... |
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| Edge sensitive set-reset flip flop |
| Accordingly, it is the object of this invention to provide an improved edge sensitive set-reset ... |
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| Master-slave multivibrator with improved metastable response characteristic |
| In accordance with the present invention, a master-slave flip-flop device having a master segment ... |
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| Arbiter circuits with metastable free outputs |
| The two-input arbiter circuit shown in FIG. 1 includes input terminals 10 and 11 and output ... |
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| One or more input asynchronous register |
| The present invention is directed to a unique register configured like an edge-triggered "D" type ... |
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| Fast sense amplifier |
| With reference to FIG. 1 there is shown a sense amplifier 10. An NPN transistor 11 has a base 17 ... |
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| Slotted arbitration without time jitter in a table driven protocol |
| In accordance with the principals of the present invention a media access protocol is provided ... |
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Tile-based modular routing resources for high density programmable logic device
| Details |
Inventors: Duong, Khue;
Assignee: Xilinx, Inc. (San Jose, CA)
Primary Examiner: Tokar; Michael J.
Assistant Examiner: Roseen; Richard
Attorney, Agent or Firm: Murabito; Anthony C. Wagner Murabito & Hao, Harms; Jeanette S.
Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs. A corner tile is also provided that permits interconnection between horizontal and vertical tiles. The tiles are modular in nature so the number of tiles provided within an array and their placement are determined based on the array's particular need for routing resources, e.g., an array can have one, two or more tiles associated with a row or column of CLBs in areas of the chip where congestion is typically encountered. Each tile of the present invention can also include a plurality of switch matrices, buffers, or other active gates to facilitate signal routing. |
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DETAILED DESCRIPTION The present invention relates to signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs).
Specifically, the present invention provides signal routing resource tiles that, when coupled with existing routing resources of programmable gate arrays, allows increased CLB utilization by alleviating signal routing limitations, especially in large sized arrays.
Therefore, the routing tiles of the present invention are in addition to the existing routing resources provided by the existing macro cell library.
The routing resource tiles of the present invention are modular.
In effect, they are resource "cells" that can be freely placed by the FPGA designer within the FPGA array.
The tiles are easily replicated so that gate array devices can have one, two or more tiles associated with selected rows or columns of the semiconductor device to significantly increase routing resources in areas of the array where logic designers expect routing congestion to occur upon programming.
Since the tiles of the present invention are modular, it is possible to replicate the tiles across the array of the integrated circuit.
Use of modular tiles can thus increase routing resources including high speed transmission lines even as process improvements permit an increase in CLB density or as new families of devices are introduced.
By providing a separate routing resource tile, rather than modifying the CLB structure, the present invention allows CLB array size to be significantly increased for new FPGA families (developed in a relatively short period of time) while advantageously using existing logic function libraries.
Since routing resource tiles are modular, it is possible to minimize the size of the integrated circuit device and at the same time utilize a higher percentage of the available CLBS
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