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Use of a cache ownership mechanism to synchronize multiple dayclocks
| Details |
Inventors: Federici, James L.; Vartti, Kelvin S.; Malek, Robert M.; Boone, Lewis A.;
Assignee: Unisys Corporation (Blue Bell, PA)
Primary Examiner: Gossage; Glenn
Assistant Examiner: Peugh; Brian R.
Attorney, Agent or Firm: Johnson; Charles A., Starr; Mark T. Nawrocki, Rooney & Sivertson, P.A.
A method of and apparatus for improving the efficiency of a data processing system employing multiple dayclocks using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from dedicating a separate individual dayclock to each of the multiple instruction processors within the data processing system thereby decreasing access time and user queuing. These individual dayclocks are each incremented at one microsecond intervals. However, these individual dayclocks require periodic synchronization to avoid system level time-tagging problems. This synchronization occurs at 20 microsecond intervals using the cache coherency maintenance hardware of the system. |
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DETAILED DESCRIPTION The present invention overcomes the problems found in the prior art by providing a method of and apparatus for synchronizing multiple dayclocks within a multiple processor system having hierarchical memory.
This synchronization process is basically provided by the cache memory coherency maintenance facilities.
The preferred mode of the present invention includes up to four main memory storage units.
Each is coupled directly to each of up to four "pod"s.
Each pod contains a level three cache memory coupled to each of the main memory storage units.
Each pod may also accommodate up to two input/output modules.
Each pod may contain up to two sub-pods, wherein each sub-pod may contain up to two instruction processors.
Each instruction processor has two separate level one cache memories (one for instructions and one for operands) coupled through a dedicated system controller, having a second level cache memory, to the level three cache memory of the pod.
Each instruction processor has a dedicated system controller associated therewith.
A separate dayclock is located within each system controller.
Unlike many prior art systems, both level one and level two cache memories are dedicated to an instruction processor within the preferred mode of the present invention.
The level one cache memories are of two types.
Each instruction processor has an instruction cache memory and an operand cache memory.
The instruction cache memory is a read-only cache memory primarily having sequential access.
The level one operand cache memory has read/write capability.
In the read mode, it functions much as the level one instruction cache memory.
In the write mode, it is a semi-store-in cache memory, because the level two cache memory is also dedicated to the instruction processor.
In accordance with the present invention, the level two cache memory is of the store-in type.
Therefore, the most current value of an operand which is modified by the corresponding instruction processor is first located within the level two cache memory
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