Floppy disk drive with local processor control |
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Insert for blocking operation of the disc write switch in use of computer diskettes |
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Capacitor case cover disc seal and venting means |
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Intermediate output buffer circuit for semiconductor memory device |
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Means and method for controlling eluent gradient in liquid chromatography |
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Transistor differential amplifier circuit |
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Data processing system having centralized bus priority resolution |
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Data processor with improved loop handling utilizing improved register allocation |
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Vector processor for processing database without special tags for vector elements
| Details |
Inventors: Kojima, Keiji; Torii, Shunichi; Sakata, Akiharu;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Zache; Raulfe B.
Assistant Examiner:
Attorney, Agent or Firm: Kenyon & Kenyon
A vector processor includes a memory for storing vector data, a processing circuit, a fetch circuit for sequentially fetching elements of a first vector data to be processed from the memory and supplying them to the processing circuit, a generation circuit for generating tag information to designate the fetched vector elements, and a write circuit responsive to the process result by the processing means for writing the tag information generated for the element having a predetermined process result into the memory as one element of a second vector data. |
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DETAILED DESCRIPTION It is an object of the present invention to provide a vector processor which does not need to add tag information and has a high processing efficiency. The above object is achieved by providing means for generating information which enables identification of each vector element in a vector operand such as vector element numbers in an operation unit or main memory addresses of vector elements and storing such information in the main memory as tags for the operation result. A part number of a part name table 701 is stored in a first input operand X and a part number of a price table 702 is stored in a second input operand Y, and the element of X and the element of Y are compared. If both elements are equal, a pair of operand counters of the input operands are generated as tag information to identify both elements and they are outputted as elements of a third output operand Z. The operands X and Y and the counters i and j are initially "1" and the comparison of X(1) and Y(1) is equal (P2=P2). Accordingly, the pair (i, j) or (1, 1) is stored as Z(1). Then, the operand counters i and j are incremented by one and X(2) and Y(2) are compared. Since they are not equal (P3<P5), the pair (2, 2) is not stored and only the smaller operand counter i is incremented by one, and similar operation is repeated. When the operand counters i and j are 3 and 4, respectively, they are gain equal (P8=P8) and the pair (3, 4) is stored as (Z2). The output vector Z shows the lines of two tables to be joined which have the same part number. A join table may be prepared based on the vector Z. Since the tag information for identifying the line is derived from the operand counter which indicates the progress status of the vector operation, there is no need to previously add the tag information to the vectors X and Y.
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