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Home CPUs Video-signal-time-base-compression-apparatus

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 Video signal time base compression apparatus

Details
Inventors: Kawakami, Toshikatsu; Fujimori, Toshimitsu;
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Primary Examiner: Kostak; Victor R.
Assistant Examiner:
Attorney, Agent or Firm: Stevens,Davis, Miller & Mosher

A video signal processing apparatus is provided which can be used when a transmitted video signal is displayed on a screen or a CRT having an aspect ratio (e.g. 9:16) different from an aspect ration (e.g. 4:3) of the transmitted video signal. When the video signal is time-base-compressed and displayed on the screen or CRT, a memory is used to store the digitally converted video signal. The video signal is written into the memory every two scan periods and is read out of the memory every two scan periods, thereby executing a double-speed scan conversion and also enabling time-base-compression to be performed. Accordingly, an optimum display state of video signals of various aspect ratios can be obtained by a small number of memory elements.

DETAILED DESCRIPTION In consideration of the above subjects, it is an object of the invention to provide a video signal processing apparatus in which a circuit for the simple double speed and a circuit for the time base compression which have independently been executed are constructed as a single circuit and the number of memories is reduced and a circuit construction is simplified.
To solve the above subjects, according to a video signal processing apparatus of the invention, the writing operation into a memory is processed every 2H and the reading operation from the memory is also processed every 2H, so that the circuit for the simple double-speed and the circuit for the time base compression which have independently been executed can be constructed as a single circuit, the number of memories which are used can be reduced, and the peripheral circuit construction can be simplified.
According to the invention, by using the above construction, the number of memories which are used is reduced, the peripheral circuit construction can be efficiently realized, and it is possible to contribute to a decrease in costs.



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