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 Virtual access cache protection bits handling method and apparatus

Details
Inventors: Wang, Wen-Hann;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Coleman; Eric
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman

A protection update buffer in conjunction with a cache memory that stores data, protection information and data line tags. The protection update buffer also stores cache address tags. By storing cache tags in the protection update buffer, the protection update buffer may alert the cache memory of lines that have had protection bits change. Also, by further storing data protection information in the protection update buffer, it is possible for the protection update buffer to provide correct protection information for cached data. If writing a tag and/or data protection information to the protection update buffer causes an overflow of the protection update buffer, then the associated cache is flushed and the entries of the protection update buffer are cleared.

DETAILED DESCRIPTION FIG.
1 illustrates a block level diagram of a portion of a computer system incorporating the present invention.
The computer system of FIG.
1, includes a virtual address cache 130, a physical address cache 150, and an external physical memory 170.
The virtual address program execution core 100 receives instructions or data from either virtual address cache 130, physical address cache 150, or external physical memory 170.
Virtual address cache data bus 139 passes data between the program execution core 100 and virtual address cache 130.
The internal data bus 189 is used to transfer data between program execution core 100, physical address cache 150, and the CPU data bus interface unit 180.
Other embodiments (as shown in FIG.
3) combine the internal data bus 189 and the virtual address cache data bus 139 to a single shared bus.
Protection information associated with virtual address cached data is passed between the virtual address cache 130 and the program execution core 100 on the virtual address cache protection bits bus 131.
In this way, data accessed from the virtual address cache 130 may have associated protection information delivered along with the data.
If the data desired by the program execution core 100 is not contained in the virtual address cache 130, a virtual-to-physical address translation (using the address segmentation unit 110 and/or the address paging unit 120) may be required.
If the address segmentation unit 110 or address paging unit 120 are used to generate a physical address for the desired data, their respective segmentation protection bits bus 111 or paging protection bits bus 121 pass associated data protection information to the program execution core 100.
Most address segmentation units or address paging units contain protection information for only some of the memory segments or pages.
Periodically, external physical memory is accessed to load the appropriate protection information for a new page or segment from an externally stored descriptor table



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