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Wide band constant duty cycle pulse train processing circuit
| Details |
Inventors: Hoppe, Karl-Heinz;
Assignee: Robert Bosch GmbH (Stuttgart, DE)
Primary Examiner:
Assistant Examiner:
Attorney, Agent or Firm:
A wide band constant duty cycle pulse train processing circuit where the pulse train frequency varies is proposed. The circuit serves primarily to obtain the basic clock in decoding signals encoded in the bi-phase mark code and includes a pulse-shaping or wave-shaping circuit, which receives the data signals and is followed by a low-pass filter; a differential amplifier circuit, one input of which is connected to the output of the low-pass filter and the other input of which is connected to a variable voltage source; and a current source, controlled by the differential amplifier circuit, at the input of the wave-shaping circuit determining the pulse length. The closed control loop between the output and the input of the wave-shaping circuit that determines the pulse length causes the duty cycle established at the variable voltage source to be maintained over wide ranges of the incident pulse train frequency. |
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DETAILED DESCRIPTION In FIG.
1, a binary signal train is shown, which has three equal values, namely binary "0", proceeding from left to right, initially in succession.
A train of binary "1" and "0" signals in alternation then follows.
This signal train, encoded by bi-phase marking, results in not only a change in the signal states between a first characteristic level and a second characteristic level at the boundaries of each bit cell, but also a signal edge or level change in the middle of each bit cell which represents a binary "1".
A circuit for generating a pulse train with a constant duty cycle at a varying pulse train frequency is shown in FIG.
2.
In this circuit, the trigger input of a monostable multivibrator, or flip-flop (MFF) 1 is connected to the data input 2.
The direct input of a differential amplifier 3 is connected via an RC element comprising the resistor 4 and the capacitor 5 with the inverting output Q of the MFF 1.
The junction of a voltage divider comprising the resistors 6, 7 is connected via the resistor 8 with the inverting input of the differential amplifier 3.
From the output of the differential amplifier 3, a feedback circuit with low-pass characteristics and comprising a parallel circuit of a resistor 9 and a capacitor 10 leads to the inverting input of the differential amplifier 3.
From the output of the differential amplifier 3, there is a connection via a Zener diode 11 with the base of a transistor 12, the collector of which is connected via a resistor 13 with the network 14 of the MFF 1 that determines the time constant.
The base of the transistor 12 is supplied via a resistor 16 with a DC voltage, and the emitter of the transistor 12 is also connected with a source of DC voltage.
A diode 15 is disposed between the inverting input and the direct input of the differential amplifier 3.
The cathode of the diode 15 is connected with the direct input, and the anode is connected with the inverting input.
OPERATION With each positive edge of the data signal at the data input 2, the MFF 1 is triggered and initially emits an unchanged pulse train, as long as the regulating circuit, which comprises the low-pass filter 4, 5, the differential amplifier 3, the transistor 12 and the voltage divider 6, 7, has not yet started up
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