Bus arrangement for interconnecting circuit chips
For interconnecting a plurality of integrated circuit chips, optical waveguide buses are provided in a substrate. Each optical bus consists of a feeder guide and a parallel signal guide which merge at... Read More
Inventors: Gfeller, Fritz R.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Optical fiber sensor with localized sensing regions
In accordance with the present invention, there is provided a coupling mechanism for a non-identical dual core fiber. The desired sensitivity can be localized to selected lengths of the fiber and can ... Read More
Inventors: Domash, Lawrence H.;, Assignee: Corning Incorporated (Corning, NY) |
Optical transmission network with frequency locking means
I claim: 1. Optical transmission network, comprising an optical transmission medium with one or more optical fibers, to which, at one side, one or more first optical transceivers are connected and to ... Read More
Inventors: van Deventer, Mattijs O.; Bekooij, Johan P.;, Assignee: Koninklijke PTT Nederland N.V. (Groningen, NL) |
Wide dynamic range optical link using DSSC linearizer
OF THE INVENTION Referring to FIG. 1, the present invention comprises a laser source 10 which provides a coherent lightwave carrier signal upon which information is carried. The lightwave carrier is ... Read More
Inventors: Gertel, Eitan; Sipes, Jr., Donald L.;, Assignee: AEL Industries, Inc. (Lansdale, PA); Amoco Corporation (Chicago, IL) |
Apparatus for working leads of electrical components
I claim: 1. In an apparatus for working leads of electrical components having an inlet unit with a guideway and fixedly supported on a base-plate, two tools designed for operation with said inlet unit... Read More
Inventors: Weresch, Thomas;, Assignee: |
Press fit pinless latching shroud
In accordance with the present invention, a pinless shroud is provided that substantially eliminates or reduces disadvantages and problems with prior connectors. A shroud for retaining a connector on ... Read More
Inventors: Martin, Edward G.;, Assignee: DSC Communications Corporation (Plano, TX) |
Flexible module interconnect system
Referring first to FIG. 1, and in accordance with this invention, a backplane 10 is provided having a plurality of module receiving slots 12 formed therein. Each slot 12 has a plurality of pins 14 wh... Read More
Inventors: Oliver, Christopher J.;, Assignee: Cabletron Systems, Inc. (Rochester, NH) |
High-density erasable programmable logic device architecture using multiplexer interconnections
It is an object of this invention to provide a PLD architecture in which power consumption is reduced by eliminating programmable elements from the PIA. It is a further object of this invention to pro... Read More
Inventors: Pedersen, Bruce B.; Chiang, David; Heile, Francis B.; McClintock, Cameron; So, Hock-Chuen; Watson, James A.;, Assignee: Altera Corporation (San Jose, CA) |
PLD with selective inputs from local and global conductors
It is an object of the present invention to provide an improved PLD integrated circuit that combines low power circuitry with high performance interconnect architecture to achieve higher logic densiti... Read More
Inventors: Watson, James A.; McClintock, Cameron R.; Randhawa, Hiten S.; Li, Ken M.; Ahanin, Bahram;, Assignee: Altera Corporation (San Jose, CA) |
Programmable logic array with local and global conductors
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuits in which signal conductors are in... Read More
Inventors: Pedersen, Bruce B.; Cliff, Richard G.; Ahanin, Bahram; Lytle, Craig S.; Heile, Francis B.; Veenstra, Kerry S.;, Assignee: Altera Corporation (San Jose, CA) |
Valid flag for disabling allocation of accelerated graphics port memory space
The above and other objects of the present invention are satisfied, at least in part, by providing in a computer system a core logic chipset that functions as a bridge between an AGP bus and host and ... Read More
Inventors: Horan, Ronald T.; Jones, Phillip M.; Santos, Gregory N.; Lester, Robert Allan; Elliott, Robert C.;, Assignee: Compaq Computer Corp. (Houston, TX) |
Address translation unit supporting variable page sizes
It is, therefore, an object of the present invention to provide an address translation unit which carries out the address translation with variable page sizes at high speed, and which can be realized ... Read More
Inventors: Kang, Hoai Sig;, Assignee: Hyundai Electronics Industries Co., Ltd. (Ichon-shi, KR) |
Four quadrant multiplying divider using three log circuits
OF THE INVENTION Referring to the figures and more particularly FIG. 1 (prior art), the circuitry illustrated therein consists of three logarithmic transfer circuits 10, 12 and 14 as disclosed in U.S... Read More
Inventors: Smith, John I.;, Assignee: |
Method and apparatus for electro-optically convoluting a one-dimensional signal
The problem of the prior art is eliminated by a method and apparatus for convoluting a signal representing a profile formed during X-ray tomography and a filter function wherein the one-dimensional im... Read More
Inventors: Baumann, Jacob S.; Geluk, Ronald J.;, Assignee: N.V. Optische Industrie "De Oude Delft" (NL) |
Exponential operation device
To attain the above-mentioned object, an exponential operation device according to the invention comprises operation means for effecting a calculation on an exponential function represented by x and y... Read More
Inventors: Yoshida, Junichi;, Assignee: Casio Computer Co., Ltd. (Tokyo, JP) |
Hardware arrangement for floating-point addition and subtraction
It is an object of this invention to provide a hardware arrangement for floating-point addition by which fast execution can be attained with a simple hardware configuration. More specifically, the pre... Read More
Inventors: Nakayama, Takashi;, Assignee: NEC Corporation (Tokyo, JP) |
Time reversal gaussian approximation filter
As shown in FIG. 1, a time reversal filter comprises a first IIR 12, a first time reversal memory 14, a second IIR 16 and a second time reversal memory 18. If time reversal is implemented by recordin... Read More
Inventors: Levien, Raphael L.;, Assignee: |
Apparatus and method for accelerating floating point addition and subtraction operations by accelerating the effective subtraction procedure
The aforementioned and other features are accomplished, according to the present invention, by providing in a floating point execution unit a relatively fast procedure for performing an effective subt... Read More
Inventors: Maheshwari, Vijay; Samudrala, Sridhar; Gavrielov, Nachum M.;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Dot matrix type serial printer
This invention has been developed for the purpose of obviating the aforesaid disadvantages of the prior art. Accordingly, the invention has as its object the provision of a dot matrix type serial prin... Read More
Inventors: Miki, Yasuhiro;, Assignee: Brother Industries, Ltd. (Nagoya, JP) |
Method of OCR template enhancement by pixel weighting
I claim as my invention: 1. The method of matching an unknown input pixel symbol with a library of enhanced pixel templates by recognition enhancement of a library of L unenhanced pixel images (I.sub.... Read More
Inventors: Avi-Itzhak, Hadar;, Assignee: Canon Research Center America, Inc. (Palo Alto, CA) |
Booth's multiplier
With these problems in mind, therefore, it is the primary object of the present invention to provide a high speed multiplier of a relatively simple circuit configuration. To achieve the above-mentione... Read More
Inventors: Tokumaru, Takeji; Kishigami, Hidechika;, Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Mixed size radix recoded multiplier
Accordingly, it is an object of the present invention to provide an improved multiplier which minimizes carry delays. Another object of the present invention is to provide an improved method and appar... Read More
Inventors: Williams, Tim A.;, Assignee: Motorola Inc. (Schaumburg, IL) |
Discrete cosine transform calculation processor
The invention consists in a discrete cosine transform calculation processor for calculating the transform of a sequence of N digital data points where N=2.sup.n and n is an integer greater than two, c... Read More
Inventors: Arnould, Emmanuel; Dugre, Jean-Pierre;, Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel (Paris, FR) |
Multi-level band-restricted waveform generator
An object of the present invention is to provide a method for generating a multi-level band-restricted waveform generator for generating the multi-level band-restricted waveform through digital proces... Read More
Inventors: Urabe, Kenzo; Akaiwa, Yoshihiko;, Assignee: Kokusai Electric Co., Ltd. (Tokyo, JP) |
Method for binary multiplication of a number by a sum of two numbers and a digital system for implementation thereof
This aim is achieved by the application of the method according to the invention wherein the multiplier expressed by two numbers--summands represented in a binary number system--is transformed paralle... Read More
Inventors: Majerski, Stanislaw;, Assignee: |
Partial product accumulation in high performance multipliers
OF THE DRAWINGS FIGS. 1' and 1A-1C show a complete 8.times.8 bit encoded binary multiplier according to the prior art. FIGS. 2A-2H show the set of cells required to implement the accumulation techniq... Read More
Inventors: Ware, Frederick A.;, Assignee: Hewlett-Packard Company (Palo Alto, CA) |
Integrated circuit fast multiplier structure
I claim: 1. A high-speed multiplier structure of MOS integrated circuit design for the multiplication of two binary words of N bits, the said structure comprising N.sup.2 elementary multipliers arrang... Read More
Inventors: Lerouge, Claude P. H.;, Assignee: International Standard Electric Corp. (New York, NY) |
Architecture for integrated concurrent vector signal processor
These and other objects, features and advantages are achieved by the concurrent vector signal processor architecture disclosed herein. The concurrent vector signal processor is a programmable integrat... Read More
Inventors: Genusov, Alexander; Friedlander, Ram B.; Feldman, Peter; Fruchter, Vlad; Jaliff, Ricardo; Mohr, Asaf; Retter, Rafi;, Assignee: Zoran Corporation (Santa Clara, CA) |
Floating point type multiplier circuit with compensation for over-flow and under-flow in multiplication of numbers in two's compliment representation
It is, therefore, an object of the present invention to realize a floating point multiplication the flow of which is processed at a high speed without any programming. Another object of the present in... Read More
Inventors: Kobayashi, Masahito; Maeda, Narimichi; Hagiwara, Yoshimune; Akazawa, Takashi; Sugiyama, Shizuo;, Assignee: Hitachi, Ltd. (Tokyo, JP); Hitachi Denshi Kabushiki Kaisha (Tokyo, JP) |
Facsimile communication device
It is an object of the present invention to provide a facsimile communication device of which system architecture is simplified and of which operability is highly improved. Accordingly, the present in... Read More
Inventors: Matsuda, Toshihiro; Moriya, Daisuke;, Assignee: Sharp Kabushiki Kaisha (Osaka, JP) |
CPUs 
