Dynamically programmable logic circuits
It is an object of the present invention to provide a programmable logic circuit which can perform, under control of program variables, a number of logic functions, using the same components. It is an... Read More
Inventors: Suarez, Ricardo; Chang, Oscar; Adam, Vladimir;, Assignee: Instituto Venezolano de Investigaciones Cientificas (IVIC) (VE) |
Emitter-coupled logic circuit
OF THE PRIOR ART Description will be hereinafter made with reference to FIG. 1 to more clearly show the drawbacks of a prior-art emitter-coupled logic circuit. In FIG. 1 of the accompanying drawings ... Read More
Inventors: Tamegaya, Yukio;, Assignee: NEC Corporation (JP) |
Apparatus and method for reducing power consumption in a computer system
A method and apparatus for reducing the power consumption of a processor in a computer system is described. The present invention includes a programming structure running on the processor that determi... Read More
Inventors: Townsley, David B.; Chow, Wing-Hong; Johnson, Michael D.; Ramalho, Helder;, Assignee: Apple Computer, Inc. (Cupertino, CA) |
Apparatus and method for displaying PMS information in a portable computer
Accordingly, it is an object of the present invention to provide an improved apparatus and method for displaying power management system (PMS) information in a portable computer. It is another object ... Read More
Inventors: Seo, Seung-Won;, Assignee: SamSung Electronics Co., Ltd. (Suwon, KR) |
Logic circuit
The invention will be described below briefly. Namely, a plurality of ROM's of a large capacity constituted by IIL circuits are prepared, and one of them is selected by the high-order bits of an input... Read More
Inventors: Furihata, Makoto; Ogura, Setsuo; Kondo, Shizuo; Minamimura, Eiji;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Control module for reducing ringing in digital signals on a transmission line
In accordance with the present invention, an electronic control module is provided that reduces ringing in the digital signals on a transmission line which has multiple transmitters, receivers, and pa... Read More
Inventors: Peterson, LuVerne R.;, Assignee: Unisys Corporation (Blue Bell, PA) |
For conditioning the input to or the output from an integrated circuit
The present invention has been developed to obviate the above-described problems and has as its first object the provision of a programmable input/output circuit connected to an input terminal or an o... Read More
Inventors: Kawana, Keiichi;, Assignee: Kawasaki Steel Corporation (Hyogo, JP) |
Apparatus for sensing data in data bus lines
It is an object to provide a data sense circuit which prevents the charge share caused by direct connection between the bit lines and the data bus lines, reduces power consumption caused by charge and... Read More
Inventors: Ahn, Seung H.;, Assignee: Hyundai Electronics Industries Co., Ltd. (Kyoungkido, KR) |
Programmable circuit arrangement
We claim: 1. A circuit which can be programmed by applying a programming voltage so that the circuit delivers a signal at its output having a predetermined binary value, comprising: input means respon... Read More
Inventors: Huse, Horst; Elmer, Werner;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Read-only memory with few programming signal lines
It is accordingly an object of the present invention to enable a PROM to be programmed using only a small number of input signals. A programmable read-only memory circuit has a programmable read-only ... Read More
Inventors: Matsubara, Hiroaki;, Assignee: Oki Electric Industry Co., Ltd. (Tokyo, JP) |
System for dynamically exchanging and matching revision information between host and terminal
An object of the present invention is to eliminate such a drawback and to provide a system for dynamically exchanging the revision information between the host and the terminal which takes matching of... Read More
Inventors: Shiga, Shoji; Katagiri, Kunihiro;, Assignee: NEC Corporation (Tokyo, JP) |
Registered logic macrocell with product term allocation and adjacent product term stealing
This invention provides a macrocell with product term allocation and adjacent product term stealing. Programmable configuration switches provide product term allocation by directing input product term... Read More
Inventors: Pedersen, Bruce B.;, Assignee: Altera Corporation (San Jose, CA) |
Apparatus and method for product term allocation in programmable logic
A programmable logic device having an allocation scheme for pooling product terms is described. In the following description, for purposes of explanation, numerous specific details are set forth, suc... Read More
Inventors: Steele, Randy C.;, Assignee: Intel Corporation (Santa Clara, CA) |
Level converter circuit for converting ECL-level input signals
It is therefore an object of the present invention to provide a level converter circuit in view of the aforementioned defects of the prior art, which is capable of reducing a propagation delay time wi... Read More
Inventors: Oguri, Takashi;, Assignee: NEC Corporation (Tokyo, JP) |
Logic gates with controllable time delay
These needs are met by providing a variable threshold voltage logic element. The threshold voltage is controllably varied, using multiplication means, summation means and Signum function means. In one... Read More
Inventors: Corcoran, John J.; Poulton, Kenneth D.;, Assignee: Hewlett-Packard Company (Palo Alto, CA) |
Programmable logic cell and array
OF DRAWING FIG. 1 depicts an array 10 of cells 20 formed in accordance with the present invention. As is apparent, the cells are arranged in a two dimensional matrix with each cell having four neares... Read More
Inventors: Furtek, Frederick C.;, Assignee: Concurrent Logic, Inc. (Sunnyvale, CA); Apple Computer, Inc. (Cupertino, CA) |
Output logic macrocell with enhanced functional capabilities
This invention provides an output logic macrocell for use with a logic block such as a programmable logic array. The output logic macrocell contains an XOR gate, an OR gate, a register, and a pluralit... Read More
Inventors: Shen, Ju; Chan, Albert L.; Shankar, Kapil; Tsui, Cyrus;, Assignee: Lattice Semiconductor Corporation (Hillsboro, OR) |
Graphics system including an output buffer circuit with controlled Miller effect capacitance
Generally, and in one form of the invention, an integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rai... Read More
Inventors: Krenik, William R.; Izzi, Louis J.;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Safestore frame implementation in a central processor
What is claimed is: 1. In a central processor including: A) data manipulation means for performing successive data manipulation operations and for making safestore information available at the conclus... Read More
Inventors: McCulley, Lowell D.; Guenthner, Russell W.; Eckard, Clinton B.; Rabins, Leonard; Shelly, William A.; Lange, Ronald E.; Edwards, David S.;, Assignee: Bull HN Information Systems Inc. (Billerica, MA) |
Refresh control for dynamic memory in multiple processor system
In accordance with one embodiment of the invention, a computer system employs three identical CPUs typically executing the same instruction stream, and has two identical, self-checking memory modules ... Read More
Inventors: Peet, Jr., Charles E.; Allison, John D.; Debacker, Kenneth C.; Horst, Robert W.;, Assignee: Tandem Computers Incorporated (Cupertino, CA) |
System and method for providing a fault tolerant computer program runtime support environment
The present invention automatically converts a non-fault tolerant software program into a fault-tolerant software program. To achieve this goal, the invention includes two separate CPUs, each having a... Read More
Inventors: Del Vigna, Jr., Paul;, Assignee: Tandem Computers, Incorporated (Cupertino, CA) |
Multiple processor synchronized halt test arrangement
An object of this invention is to provide a stable testing and debugging environment for a multiprocessor system and the ability to examine one or all processors when one or more halts. The latter aid... Read More
Inventors: Fowler, Glenn D.; Shannon, Patrick A.; Stout, Ronald L.; Yao, Jean;, Assignee: AT&T Bell Laboratories (Murray Hill, NJ) |
High-availability computer system with a support logic for a warm start
It is an object of this invention to control the assignment of the logic processors to operating status in such a manner that in the course of several start phases, i.e., warm start or restart, each l... Read More
Inventors: Wengert, Ulrich;, Assignee: Siemens Aktiengesellschaft (Berlin and Munich, DE) |
Redundant read bus for correcting defective columns in a cache memory
Generally, the present invention relates to efficiently implementing column redundancy in a cache memory architecture to reach high speed performance. The invention basically involves the use of a sep... Read More
Inventors: Gabillard, Bertrand; Girard, Philippe; Omet, Dominique;, Assignee: International Business Machines Corporation (Armonk, NY) |
Plural sensor monitoring and display device
We claim: 1. In a monitoring device for monitoring the outputs of a plurality of sensors and displaying appropriate information, said device comprising: a plurality of input gate circuits for connecti... Read More
Inventors: Green, Douglas Harry; Pickup, Joseph;, Assignee: Delphic Limited (Douglas, EN) |
Fault diagnostic distributed processing method and system
It is an object of the present invention to provide a distributed processing system which resolves problems encountered in the prior art distributed processing system, and uses a self-diagnostic teste... Read More
Inventors: Mori, Kinji; Miyamoto, Shoji; Shiraha, Takeshi;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Method and system for identification of software application faults
What is claimed is: 1. A method for identification of a fault in a software application associated with a hardware platform at a site, the software application including a plurality of processes, the ... Read More
Inventors: Batra, Jatinder Pal Singh;, Assignee: U S West Technologies, Inc. (Boulder, CO) |
System for reading system log
The inventive remote access system provides system administrators with new levels of client/server system availability and management. It gives system administrators and network managers a comprehensi... Read More
Inventors: Nouri, Ahmad; Johnson, Karl S.;, Assignee: Micron Electronics, Inc. (Nampa, ID) |
Shift register programming for a programmable logic device
The present invention describes a novel architecture to improve the performance of a programmable logic device by removing the memory cell from the signal path. In one embodiment, input signals are co... Read More
Inventors: Allen, Michael J.;, Assignee: Intel Corporation (Santa Clara, CA) |
Complementary logic input parallel (CLIP) logic circuit family
It is therefore an object of the present invention to provide a high speed complementary all-parallel FET logic circuit family. It is another object of the present invention to provide a high speed co... Read More
Inventors: Vinal, Albert W.;, Assignee: Thunderbird Technologies, Inc. (Research Triange Park, NC) |
CPUs 
