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Partially-operable driver circuit
| Details |
Inventors: Fujisawa, Yoshimitu;
Assignee: Oki Electric Industry Co., Ltd. (Tokyo, JP)
Primary Examiner: Callahan; Timothy P.
Assistant Examiner: Ton; My-Trang Nu
Attorney, Agent or Firm: Panitch, Schwarze, Jacobs & Nadel
A driver circuit comprising an output level selection circuit and a shift register is disclosed. The output level selection circuit has driving terminals, potential level input terminals and data input terminals, and an output signal having one of the different potential levels from the driving terminals in response to the data signals. The shift register includes an input terminal, an output terminal, a control terminal, a control circuit, a first shift circuit, and a second shift circuit. The first shift circuit has an input coupled to the input terminal of the shift register and the control circuit, and an output coupled to the control circuit. The second shift circuit has an input coupled to the control circuit and an output coupled to the output terminal of the shift register. The control circuit couples the input terminal to the input of the first shift stage circuit and also couples the output of the first shift stage circuit and the input of the second shift stage circuit when a control signal is in a first state. Similarly, the control circuit couples the input terminal to the input of the second shift circuit when the control signal is in a second state. |
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DETAILED DESCRIPTION It is an object of the present invention to provide a driver circuit capable of stopping the operations of unnecessary driving outputs thereof.
It is another object of the present invention to provide a driver circuit capable of dividing driving outputs thereof and operating the divided driving outputs.
The above object are generally achieved according to the present invention by a driver circuit comprising an output level selection circuit having driving terminals, potential level input terminals to which different electrical potential levels are applied and data input terminals receiving data signals, for outputting a signal having one of the different potential levels from the driving terminals in response to the data signals, an input terminal receiving an input signal, an output terminal, a control terminal receiving a control signal which has a first state and a second state, and a shift register coupled to the data input terminals of the output level selection circuit, the control terminal and the input and output terminals for generating the data signals from the input signal.
The shift register includes a first shift register circuit having an input coupled to the input terminal and an output, the second shift register circuit having the data latch circuits serially coupled each other, and a control circuit having a first terminal coupled to the input terminal, a second terminal coupled to the output of the first shift register circuit, a third terminal coupled to the input of the second shift register circuit and a control terminal coupled to the control terminal.
Each of the first and second shift register circuits has data latch circuits serially coupled each other.
The control circuit couples the first and third terminals thereof in response to the first state of the control signal and couples the second and third terminals thereof in response to the second state of the control signal.
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