Phase difference fault detector

DETAILED DESCRIPTION OF THE INVENTION Attention is now directed to FIG.
1 which provides an electrical circuit 10 of the invention.
The circuit 10 includes a heater 12, a power supply 14, transducers 16 and 18, filters 20 and 22, and a comparator 24.
Conventional components can be used for this purpose.
As indicated above, the power supply signal preferably is a voltage signal and the device signal preferably is a current signal.
These signals are shown in FIG.
1 as they are developed in the primary circuit of the transducers 16 and 18 (shown as transformers) and then inputted from the secondary circuit of the transducers 16 and 18 to the filter circuits 20 and 22.
The transducers 16 and 18 preferably have a capability to handle both the power supply signal, typically 60 Hz, and, a fault signal (i.
e.
, the current signal), which may typically appear within a 10 Khz to 100 Khz spectrum.
The filter circuits 20,22, on the other hand, are preferably high pass filters, but may be band pass filters having a lower pass level of at least 10 Khz and an upper pass level of at most 100 Khz.
The power supply signal and the device signal outputted by the filters 20 and 22 preferably are inputted to the comparator 24 through capacitive coupling i.
e.
capacitors 26 and 28.
The comparator 24 comprises the following assembly: (a) a first operational amplifier 30 that receives device signal inputs and provides a first digital logic output signal for input to a device signal inverter 32; (b) a second operational amplifier 34 that receives device signal inputs and provides a second digital logic output signal for input to a first NAND-gate module 36; (c) a third operational amplifier 38 that receives power supply signal inputs and provides a third digital logic output signal for input to a power supply signal inverter 40; and (d) a fourth operational amplifier 42 that receives power supply signal inputs and provides a fourth digital logic output signal for input to a second NAND-gate module 44.
The device signal inverter 32 receives the first digital logic output signal from the first operational amplifier 30 and provides an inverted first digital logic output signal for input to the second NAND-gate module 44