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Circuit-configuration-for-metering-pulse-recognition

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Circuit configuration for metering pulse recognition

Details

Inventors: rrer, Lukas; Bernd (Mü, nchen, DE); Kranz, Christian;
Assignee: Infineon Technologies AG (Munich, DE)
Primary Examiner: Gary; Erika A.
Assistant Examiner:
Attorney, Agent or Firm: Greenberg; Laurence A., Stemer; Werner H., Mayback; Gregory L.

A circuit configuration for metering pulse recognition includes an A/D converter that receives a signal containing metering pulses, and a digital comparator circuit for comparing the output signal from the A/D converter with a reference value. A detector unit evaluates the output signal from the comparator circuit. This means that an analog comparator can be dispensed with, and the chip area and the development complexity can be reduced.

DETAILED DESCRIPTION It is accordingly an object of the invention to provide a circuit configuration for metering pulse recognition which overcomes the above-mentioned disadvantages of the prior art apparatus this general type.
In particular, it is an object of the invention to provide a circuit configuration for metering pulse recognition which has reduced implementation complexity.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for metering pulse recognition, that includes: an input for obtaining a signal containing metering pulses of a particular frequency and a particular amplitude; an A/D converter circuit connected to the input for obtaining the signal containing the metering pulses of the particular frequency and the particular amplitude; and a detection device for recognizing and counting the metering pulses of the particular frequency and the particular amplitude.
The A/D converter circuit provides an output signal.
The detection device includes a digital comparator circuit for performing a comparison of the output signal from the A/D converter circuit with a reference value and for providing an output signal dependent upon the comparison.
The detection device includes a detector unit for evaluating the output signal from the digital comparator circuit.
In accordance with an added feature of the invention, there is provided, a level shifter that provides the signal containing the metering pulses of the particular frequency and the particular amplitude to the A/D converter circuit.
In accordance with an additional feature of the invention, a digital interpolation filter is connected between the A/D converter circuit and the digital comparator circuit.
In accordance with another feature of the invention, a limiter is connected in series with the digital interpolation filter.
In accordance with a further feature of the invention, an oversampler is connected upstream from the digital interpolation filter in order to increase a sampling frequency

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