Comparison circuit for masking transient differences

DETAILED DESCRIPTION I claim: 1.
A comparison circuit for comparing first and second binary signals which are transmitted to said comparison circuit, said comparison circuit comprising: delay means which recieves the first and second signals transmitted to the comparison circuit and delays the further transmission of the first and second signals for a predetermined time interval "d"; and comparison means, coupled to the delay means, for comparing the first and second binary signals to determine whether the first and second signals correspond to one another, said comparison means being capable of outputting a non-correspondence signal which is dependent upon whether the first and second signals correspond to one another.
2.
A comparison circuit as in claim 1, wherein said comparison means is constructed exclusively from synchronously operating circutry.
3.
A comparison circuit as in claim 1, comprising first and second inputs for each of the first and second signals, the first inputs of the first and second signals being fed into said delay means for forming versions of the first and second signals respectively delayed by the time interval, said delay means having respective first and second outputs for the respective first and second delayed versions of the signals, and said comparision means further comprising gate means having four inputs respectively fed by the first and second inputs and by the first and second outputs for forming at an output of said gate means the non-correspondence signal.
4.
A comparison circuit as in claim 3, wherein said gate means comprises a first comparison gate means fed by the four inputs for detecting when any of the first signal, the delayed version of the first signal, the inverse of the second signal, and the inverse of the delayed version of the second signal has a predetermined logic state, a second comparison gate means fed by the four inputs for detecting when any of the second signal, the delayed version of the second signal, the inverse of the first signal, and the inverse of the delayed version of the first signal has the predetermined logic state, and said gate means further comprises a combining gate means fed by the outputs of said first and second comparison gate means, for forming the non-correspondence signal when neither said first nor said second comparison gate means detects the predetermined logic state