Digital multiplexing system

DETAILED DESCRIPTION What we claim is: 1.
A digital multiplexing and demultiplexing system in which a number of incoming asynchronous low rate component signals can be time multiplexed into an outgoing single high rate signal by way of locally formed synchronous intermediate rate signals, the intermediate rate being a first multiple of the low rate and the high rate being a second multiple of the intermediate rate, the low rate signals comprising information bits and the intermediate rate signals and the high rate signal comprising information bits, frame locking bits, stuffing indication bits and stuffing bits arranged in frames, the system comprising: a.
means for stuffing the incoming asynchronous low rate signals in dependance upon the difference between their own originating timing frequencies and a local predetermined timing frequency slightly higher than all said originating timing frequencies; b.
means for providing in each of said low rate signals a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the intermediate rate signals divided by said first multiple; c.
means for inserting, in said low rate signal component blank bit slots, bits of selected value; d.
a first stage for multiplexing the low rate stuffed signals having blank bit slots therein and bits of selected value inserted in said slots into the intermediate rate signals whereby the information bits of the low rate stuffed signals are multiplexed into the information bits of said intermediate rate signals and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the intermediate rate signals; e.
means for providing in each of said intermediate rate signals a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the high rate signal divided by said second multiple; f.
means for inserting, in said intermediate rate signals component blank bit slots, bits of selected value; and g