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Enhanced time of arrival method |
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Traffic distribution analysis in a land mobile radio system |
| An object of the invention is improved monitoring and display of traffic distribution information ... |
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Concurrent wireless/landline interface apparatus and method |
| Accordingly, in accordance with an illustrative embodiment of the present invention, there is ... |
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Method and device for erasing message from wireless communication device having a paging function |
| The object of the present invention is to provide a method and a device which enable the user to ... |
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System and method for interfacing a wireless telephone to a personal computer |
| These disadvantages in the prior art are overcome in large part by a system and method according to ... |
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Communication system with fast control traffic |
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Flash-erase-type nonvolatile semiconductor storage device
| Details |
Inventors: Niijima, Hideto; Toyooka, Takashi; Satoh, Akashi; Sakaue, Yoshinori;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Gordon; Paul P.
Assistant Examiner:
Attorney, Agent or Firm: Truelson; Roy W., Bussan; Matthew J.
An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the validity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there. |
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DETAILED DESCRIPTION An object of the present invention is to provide an efficient redundant architecture for a flash-erase-type nonvolatile semiconductor storage device, and a method capable of improving the efficiency of the entire device. Another object of the invention is to provide an efficient method of distinguishing defective sectors and avoiding the use of those sectors in an external storage system employing a flash-erase-type nonvolatile semiconductor storage device. The above-described objects can be attained by taking advantage of the fact that in a semiconductor external storage system the inside of a sector is accessed serially. That is, memory cells on a word line of a flash-erase-type nonvolatile semiconductor storage device are associated with a sector of a semiconductor external storage system, and all the memory cells on that word line are activated every time the sector is accessed. The term "sector" includes the areas for storing system data such as ECCs. In addition to the data area, which is necessary for allowing the semiconductor external storage system to store user data, a tag area including areas for storing defective memory cell information and ECCs is connected to this word line. The data area and the corresponding tag area are activated at the same time, because they share the same word line. But they can be erased separately because they are formed in separate wells. That is, even when a data area is erased, the corresponding tag area is retained and the defective memory cell information and other data are not destroyed. Information in the tag area is written at the stage of the chip test that is performed after manufacture. The system refers to this information at every access to the sector, thereby skipping defective memory cells. When the system detects an unrecoverable error, it writes predetermined data to the tag area to avoid subsequent access to that sector. According to specific features of the invention, a flash-erase-type nonvolatile semiconductor storage device is constituted so that a memory cell array is physically divided into a data area and a tag area with shared word lines, and so that those two areas can separately be erased en bloc
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