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 High power unipolar FET switch

Details
Inventors: Chang, Hsueh-Rong; Gupta, Rajesh;
Assignee: Rockwell Science Center, LLC (Thousand Oaks, CA)
Primary Examiner: Lee; Eddie
Assistant Examiner: Lee; Eugene
Attorney, Agent or Firm: Koppel, Jacobs, Patrick & Heybl

A high power unipolar FET switch has an N- drift layer; a layer of metal contacts the drift layer via an ohmic contact to provide a drain connection for the FET. Each switch cell has a pair of trenches recessed into the drift layer and separated by a mesa region. Oxide layers line the walls and bottom of each trench, which are each filled with a conductive material; the conductive material in each trench is connected together to provide a gate connection for the FET. A shallow P region extends from the bottom of each trench into the drift layer and around the trench corners. A layer of metal contacts the mesa region via an ohmic contact to provide a source connection for the FET. The structure preferably operates as a "normally-off" device, with the potentials created by the work function difference between the conductive material and the N- mesa region completely depleting the mesa region. A positive gate voltage undepletes the mesa regions, creates accumulation channels adjacent to the oxide side-walls of the trenches, and modulates the mesa region, thereby turning the switch on and allowing current to flow between drain and source via the mesa region and the accumulation channels. The switch's unipolar structure enables the device to exhibit a fast switching speed with very low switching losses.

DETAILED DESCRIPTION A high power unipolar field-effect transistor (FET) switch is presented which overcomes the problems noted above.
The switch is particularly well-suited to high power switching applications, providing a very low on-resistance, a high blocking voltage, and negligible switching loss.
An N- drift layer is on an N+ layer which provides an ohmic contact to the drift layer (X+ denotes a carrier concentration of at least 1.
times.
10.
sup.
18 /cm.
sup.
3, X- denotes a carrier concentration of less than 5.
times.
10.
sup.
16 /cm.
sup.
3).
A layer of metal on the N+ layer provides a drain connection for the FET.
A pair of trenches are recessed into the drift layer opposite the N+ layer; the trenches are separated by a mesa region comprised of that portion of the N- drift layer found between the trenches.
Oxide layers line the walls and bottom of each trench, which are each filled with a conductive material.
A second layer of metal connects the conductive material in each of the trenches together to provide a gate connection for the FET.
A shallow P region extends from the bottom of each trench into the drift layer and around the corners formed at the intersections of its respective trench's oxide side-walls and its oxide bottom.
A second N+ layer is on the N- drift layer within the mesa region which provides an ohmic contact to the mesa region, and a third layer of metal contacts the second N+ layer to provide a source connection for the FET.
The structure is preferably arranged so that the switch operates as a "normally-off" device; i.
e.
, current is prohibited from flowing between drain and source when the voltage applied to the gate connection is zero.
This is accomplished by making the width and doping concentration of the mesa region such that, with no voltage applied to the gate, the mesa region is completely depleted by the potentials created by the work function difference between the conductive material and the N+ material in the mesa region.
The structure can also be arranged to operate as a "normally-on" device by making the mesa region so wide or its doping concentration so high that a negative gate voltage is required to completely deplete the mesa region



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