Memory timing and control apparatus

DETAILED DESCRIPTION The above and other objects and advantages of the present invention are achieved in a preferred embodiment of the present invention in which one, two or more rows of memory chips are contained on a memory option board which plugs into a basic logic board (BLB) of a data processing system.
The base logic board includes the system's main memory processing units and other control and logic support circuits.
According to the teachings of the present invention, the memory option board is constructed to include within a control section a programmable read only memory (PROM) circuit which is connected to receive from the different units of the basic logic board, a predetermined address portion of each main memory address in addition to refresh and timing signals.
The PROM is coded in a predetermined manner for generating row address select (RAS) pulse output signals to a row or block of random access memory chips of the board's memory section designed by the predetermined address portion.
The pulse widths of the output signals are established by the widths of the input timing signals applied to an enabling input of the PROM.
The same memory board can be used to expand the capacity of main memory by different amounts as a function of the PROM coding constructed with different numbers of rows of chips.
This greatly enhances memory security and maintains system integrity since a memory board with a particular memory capacity can only be accessed by a PROM specially coded to provide that capacity.
Also, the pulse width of the PROM output signals can be increased or decreased as required for accommodating different types of memory chips (e.
g.
64K or 256K) by simply increasing or decreasing the width of the timing signals applied to the PROM enabling terminal.
Additionally, as mentioned, the basic main memory resides on the basic logic board and provides a given addressing capacity.
When the predetermined address portion of the memory address specifies an address within the basic main memory, the PROM apparatus automatically inhibits its generation of output signals thereby ensuring proper memory operation without requiring any additional circuits