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| Circuit for discriminating received signal modulation type |
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Mode detection circuit for a dual purpose analog input
| Details |
Inventors: Hafner, Warren G.;
Assignee: Pitney Bowes Inc. (Stamford, CT)
Primary Examiner: Zazworsky; John
Assistant Examiner:
Attorney, Agent or Firm: DeSha; Michael J., Pitchenik; David E., Scolnick; Melvin J.
A mode detection circuit is disclosed that provides a high or low digital output signal to an associated circuit analog dependent upon the corresponding input signal. The input signal to the mode detection circuit will determine whether the mode of the input signal and associated circuit is to be external or internal. In this embodiment, the input of the mode detection circuit receives either a first voltage in the internal or a second voltage in the external mode which is lower than the first voltage. Thus, when the input voltage to the circuit is the first voltage, there is provided at the output a digital output that is high. In this embodiment, a high digital output signal would mean that the associated circuit with the detection circuit would be in the internal mode. On the other hand, when the analog input signal is the second voltage, there would be provided at the output of the detection circuit a low digital output signal which would mean that the associated circuit would be in the external mode. Accordingly, this circuit utilizes digital detect logic to which network (i.e. external or internal) of the associated circuit is to be utilized depending upon the voltage level which is provided at the input of the mode detection circuit. |
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DETAILED DESCRIPTION Referring to the drawing, a mode detection circuit in accordance with the present invention is indicated generally at 10.
The mode detection circuit 10 includes an input terminal 12 for receiving an analog input voltage.
The analog input voltage may be obtained from an external voltage source to be divided by an internal resistor network or from an external resistor network, as desired.
A first resistor 14, which forms part of a voltage divider network 16, couples the input terminal 12 to the gate terminal of a field effect transistor in the form of a P-channel MOSFET 18.
The voltage divider network 16 includes a second resistor 20 electrically coupled to the gate terminal of the P-channel MOSFET 18 and to the drain terminal of a field effect transistor in the form of an N-channel MOSFET 22.
The source terminal of the MOSFET 22 is grounded and the gate terminal is coupled to a mode output terminal 24.
The source terminal of the P-channel MOSFET 18 is electrically coupled to another voltage divider network 26, specifically at point 28 between electrically coupled resistors 30 and 32.
The other end of resistor 32 is grounded and the other end of resistor 30 is electrically coupled to a reference terminal 34 which receives the reference voltage V.
sub.
DD, which may be, e.
g.
, the chip supply voltage.
The reference terminal 34 is coupled to the mode output terminal 24 through a current limiting resistor 36.
The mode output terminal 24 is also electrically coupled to the drain terminal of a field effect transistor in the form of an N-channel MOSFET 38.
The gate terminal of the N-channel MOSFET 38 is coupled to the drain terminal of the P-channel MOSFET 18 and the source terminal of the N-channel MOSFET 38 is grounded and coupled to the drain terminal of the P-channel MOSFET 18 through a biasing resistor 40.
In operation, when the analog input voltage present at input terminal 12 is less than the voltage V.
sub.
DD divided by the voltage divider network 26 (R3/R3+R4) minus the threshold voltage of P-channel MOSFET 18, the P-channel MOSFET 18 conducts, applying a positive voltage to the gate terminal of the N-channel MOSFET 38 and causing it to turn on
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