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Home Cell Phones Single-chip-GPS-receiver-digital-signal-processing-and-microcomputer

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Details
Inventors: Lau, Chung Y.; Martin, Kreg A.; Lake, Gary W.;
Assignee: Trimble Navigation Limited (Sunnyvale, CA)
Primary Examiner: Park; Collin W.
Assistant Examiner:
Attorney, Agent or Firm: Law Offices of Thomas E. Schatzel

An embodiment of the present invention combines, on a single integrated circuit, an eight channel GPS receiver, a 68330-type microprocessor, a 68681-type DUART serial communications controller, an analog-to-digital converter, a real-time clock, a random access memory and a boot read-only memory. A system integration module and inter-module bus allow tri-state control of the microprocessor such that a commercially available 68332-type emulator may be used for software development.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG.
1 illustrates a GPS digital integrated circuit (IC) embodiment of the present invention, referred to herein by the general reference numeral 10.
The IC 10 carries out the digital processing aspects of a GPS navigation system, including GPS code correlation and position and velocity calculation, local oscillator frequency synthesis, user keyboard and display interfacing, and other digital signal processing (DSP) and input/output (I/O) functions.
IC 10 is implemented on a single semiconductor chip which may be physically laid out and fabricated on the surface of a silicon substrate, as shown in FIG.
2.
Commercial standard-cell high-performance computer-core CMOS semiconductor fabrication processes and packaging facilities available in the United States, such as provided by Motorola Semiconductor (Phoenix, Ariz.
), may be successfully used to build IC 10.
IC 10 is preferably implemented using a commercially available semiconductor fabrication technology such as advanced, triple-metal, 0.
8 micron CMOS processes directed at high performance and low power consumption.
A 144-pin thin plastic quad flat-pack (TQFP) is preferably used to package IC 10.
FIG.
1 shows that IC 10 comprises a pair of IC pin multiplexers 12 and 14, a dual universal asynchronous receiver transmitter (DUART) 16, a read only memory (ROM) 18, a random access memory (RAM) 20, a microcomputer (CPU) 22, a global channel controller 24 and a set of eight GPS receiver channels 26-33 for demodulating carrier signals simultaneously received from a plurality of orbiting GPS satellites.
IC pin multiplexers 12 and 14 make it possible for a 144-pin TQFP package to contain IC 10.
Since not all input/output signals associated with IC 10 need to be simultaneously available to the external interface, some pins are configurable to serve more than one function.
The use of standard cell devices can substantially simplify the task of implementing IC 10.
DUART 16 is preferably a standard cell device, for example the Motorola 68681 DUART



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