Six channel digital demodulator

DETAILED DESCRIPTION It is a principal object of the present invention to provide a novel programmable digital demodulator having a code error channel, a signal level channel and a phase or frequency error channel.
It is a principal object of the present invention to provide a novel programmable digital demodulator implemented on a single chip and capable of processing several different data formats in modulated or unmodulated form.
It is another principal object of the present invention to provide a digital demodulator which does not require hardware reconfiguration to accomplish multiple uses.
It is another object of the present invention to provide a novel demodulator circuit capable of processing independent pseudo noise (PN) modulation codes and data rates.
It is a general object of the present invention to provide a novel programmable digital demodulator that is simple and reliable and easily implemented on one single very large scale integrated circuit with other components.
According to these and other objects of the present invention there is provided a novel digital demodulator which comprises three despreaders connected to the input data stream and having plural outputs which define the code channel, the level channel and the phase channel.
The real and imaginary channel outputs from the despreaders are connected to individual accumulate and scale circuits which operate as data rate filter means and have real and imaginary outputs defining six channels The six channel outputs from the accumulate and scale circuits are coupled to three multiplexors and the outputs of the three multiplexors are coupled to decision directed inverters in a manner which provides a clock error signal, a signal level used for acquisition and track and a carrier error signal.