System and method for simulation of integrated hardware and software components

DETAILED DESCRIPTION In accordance with the preferred embodiments of the present invention, a system and methods for simulation of integrated hardware and software components are provided.
The system includes a cycle-accurate simulator where X-number of simulator cycles is equivalent to Y-number of cycles on a simulated hardware component.
For example, one cycle-accurate simulator cycle is equal to 0.
1 cycles on a simulated hardware component.
The cycle-accurate simulator models stages of an operation execution pipeline for a desired hardware component (e.
g.
, a central processing unit).
The cycle-accurate simulator may indicate how long an operation takes to execute and may indicate the timing and sequence of operations as they occur.
The cycle-accurate simulator is preferably event driven, and events are used to determine timing behavior and interactions of hardware and software components in a simulation.
The cycle-accurate simulator also may be used in an "instruction timing" mode, where the number of cycles required for a general operation is determined, but the order or timing of individual operations that make up the general operation are not simulated.
The system further includes a simulator library for modeling and verifying hardware components of a desired electronic device.
The simulator library may include built-in models for simulating multiple internal and external hardware components (e.
g.
, central processing units, memory, memory management units, caches, timers, universal asynchronous receiver transmitters and digital signal processors).
The built-in models return a number of cycles on the cycle-accurate simulator executed for a desired simulated operation.
The simulator library may also include simulator interface routines for setting a clock for a simulated component to a new clock speed, coordinating between a simulator library clock and a cycle-accurate simulator clock, handling events that occur before or during a current clock cycle, changing interrupt vectors and interrupt priority levels, providing notification of changes in registers during a simulated operation, or for setting one or more individual sub-components (e