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 Add-compare selection circuit

Details
Inventors: Lee, Sang-Bong;
Assignee: Brother Kogyo Kabushiki Kaisha (Nagoya, JP)
Primary Examiner: Phu; Phuong
Assistant Examiner:
Attorney, Agent or Firm: Oliff & Berridge, PLC

A high-speed add-compare selection apparatus, for a Viterbi algorithm processing apparatus having a branch metric calculator and a metric memory, is described. First and second previous metric values are supplied from the metric memory to first and second registers. The first previous metric value from the first register and a branch metric value of the present state calculated by the branch metric calculator are added, as are the second previous metric value from the second register and a branch metric value of the next state calculated by the branch metric calculator. The values obtained are compared and a survival metric value calculated accordingly.

DETAILED DESCRIPTION An object of the present invention is to provide an apparatus and method for processing a Viterbi algorithm, which increases the processing speed of the computationally complex ACS portion, thereby reducing power consumption.
Another object of the present invention is to provide a small high-speed Viterbi algorithm processing apparatus by divisionally designing the Viterbi algorithm into a portion to be processed by a digital signal processor and another portion to be processed by hardware according to the contents of the algorithm so as to increase the efficiency.
In one aspect of the invention, a high-speed add-compare selection circuit for a Viterbi algorithm processing apparatus having a branch metric calculator and a metric memory includes: first and second registers for temporarily storing first and second previous metric values read from the memory; a first adder for adding the first previous metric value from the first register and a branch metric value of the present state calculated by the branch metric calculator; a second adder for adding the second previous metric value from the second register and a branch metric value of the next state calculated by the branch metric calculator; and a comparator for comparing the outputs of the first and second adders and calculating a survival metric value accordingly.
The high-speed add-compare selection circuit may also be used as part of a Viterbi equalizer having a Euclidian value calculator.
In this case, the first and second adders add metric values from the registers with Euclidian values from the Euclidian value calculator in place of the branch metric values from the branch metric calculator.
Advantageously, the add-compare selection circuit allows for faster Viterbi processing time as compared to the conventional art.
The improvement in processing time stems from the reduction in the number of metric memory accesses required to read metric value data, and the attendant reduction in the number of clock cycles needed to compute survival metrics



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