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Apparatus and method for processing a picture-in-picture video signal
| Details |
Inventors: Do, Young S.;
Assignee: Samsung Electronics Co., Ltd. (Kyungki-do, KR)
Primary Examiner: Groody; James J.
Assistant Examiner: Cohen; Cheryl
Attorney, Agent or Firm: Sughrue, Mion, Zinn, Macpeak & Seas
The present invention relates to an apparatus and method for processing a picture-in-picture video signal for PIP display of a compressed sub-picture displayed within a main picture on advanced TV receivers. More particularly, the present invention relates to the apparatus and method for processing a PIP video signal of advanced TV systems which use real video data lines, as opposed to artifically generated lines of video data, as the interleaving line to interleave the present field being compressed, when vertically compressing a sub-picture video signal. Accordingly, the present invention provides a hardware of simple constitution and a PIP display with advanced resolution. |
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DETAILED DESCRIPTION Therefore, to solve the above problems, it is an object of the present invention to provide a method for processing a PIP video signal in order to obtain an advanced resolution of PIP display, using a real, as opposed to an artificial or compressed, video signal as an interleaving signal when pictures are vertically compressed in PIP circuits for advanced TV systems.
It is another object of the present invention to provide a circuit for vertically compressing a video signal, in which the video signal is compressed vertically according to an improved method.
It is a further object of the present invention to provide an apparatus for processing a PIP video signal for advanced TV systems, which apparatus has hardware of simple constitution and further has an advanced resolution PIP display, whereby the apparatus uses a circuit for vertical compression in accordance with the present invention.
The above and other objects are accomplished by an apparatus for processing a PIP video signal in accordance with the present invention.
The apparatus comprises a memory for storing a sub-picture signal and reading the stored signal; a vertical compressing unit synchronized with a horizontal sync signal of the sub-picture signal and for controlling the memory to store lines of the sub-picture signal by units of two subsequent lines and to not store an incoming line of the two lines; a controller for inputting to the memory a predetermined write clock and a read clock, the read clock being faster than the write clock, in a ratio given by the amount that the sub-picture is horizontally compressed; and a composite processor for composing the compressed sub-picture signal read from the memory in conformity to a main-picture video signal and the read clock.
Other features of the present invention are achieved by a circuit for vertical compression of a video signal, wherein the circuit comprises a field memory for storing and reading the video signal in field units, and a vertical compressing unit for synchronizing with a horizontal sync signal of the video signal and controlling the memory to store the lines of the video signal in units of two subsequent lines and to not store an incoming line of the two lines
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