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 Autotracking feedback circuit and high speed A/D converter using same

Details
Inventors: Wang, Chien Kuo; Huang, Chung Chin;
Assignee: Macronix International Co., Ltd. (Hsinchu, TW)
Primary Examiner: Shingleton; Michael B
Assistant Examiner:
Attorney, Agent or Firm: Haynes; Mark A. Haynes Beffel & Wolfeld LLP

A bias circuit produces a common mode bias voltage that relies upon active, auto tracking feedback responsive to the reference voltage, such as analog ground, and to the common mode bias voltage to generate a common mode voltage for a differential amplifier. The bias circuit supports high-speed operation, and is stable with variations in temperature, manufacturing processes, and with shifts in the supply voltages. In one embodiment, the bias circuit comprises an operational amplifier and a feedback amplifier that has a common mode bias terminal coupled to the output of the operational amplifier and arranged in a feedback loop with the operational amplifier. The output of the operational amplifier is used as a common mode bias voltage for a differential amplifier. The feedback amplifier is designed to match the differential amplifier for which the common mode bias voltage is being generated, and therefore produces a common mode bias voltage that automatically produces a common mode voltage for the differential amplifier that causes proper settling. A differential amplifier and a high speed analog to digital converter utilize the autotracking, active bias circuit.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention is provided with respect to FIG.
1 through FIG.
9.
FIG.
1 shows a simplified block diagram of a pipelined analog to digital converter which includes the common mode feedback circuit and the active common mode feedback bias circuit according to the present invention.
The pipelined analog to digital converter receives an analog input voltage on line 10 at the input of a sample and hold amplifier 11.
The output of the sample and hold amplifier 11 is provided to an analog to digital converter 12 which produces an output bit on line 13.
The output bit on line 13 is provided to one-bit digital to analog converter 14, the output of which is supplied to the negative terminal of a summing node 15.
The positive terminal of the summing node 15 receives the output of the sample and hold amplifier 11.
Thus the difference between the input voltage provided by the sample and hold amplifier 11 and the analog value of the digital signal on line 13 is provided as input to an interstage amplifier 16.
The output of interstage amplifier 16 is provided to a subsequent stage in the analog to digital converter, which includes stage 2 (not shown) through stage M.
The digital values provided by the stages 1 through M, are provided to error correction logic 20 which provides the output of the pipelined analog to digital controller on line 21.
According to the present invention, the sample and hold amplifier 11 includes a common mode bias terminal which receives a common mode voltage VCM.
A common mode feedback circuit 22 is coupled to the output of the sample and hold amplifier 11, and provides the common mode voltage VCM to the amplifier 11.
In addition, an active common mode feedback bias circuit 23 produces a common mode feedback bias voltage VCMB, is included which causes automatic tracking of the common mode voltage with variations in temperature, process, operating speed and other factors.
In a similar manner, the interstage amplifier 16 includes a common mode feedback circuit 24, with an active common mode feedback bias circuit 25 which provides auto tracking



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