Background-calibrating pipelined analog-to-digital converter

DETAILED DESCRIPTION Please refer to FIG.
5 illustrating a block diagram of an MDAC 50 according to the present invention.
The MDAC 50 is illustrated as a radix-2 1.
5 bit SC MDAC, however, the present invention applies to other types of pipeline stages, such as those having multi-bit operation without switched capacitors.
The MDAC 50 includes a sub-ADC 52 for converting an input analog signal V.
sub.
j to a digital code D.
sub.
j.
The sub-ADC 52 includes comparators 54, 56 and an encoder 58 capable of producing 1.
5 bit output, such as 00, "01, or 10, utilizing a reference voltage V.
sub.
r.
Detailed design and operation of the sub-ADC 52 is well known in the art.
The MDAC 50 further comprises a plurality of switches 60 selectively connecting a first capacitor 62, and second capacitors 64, 66, 68 between the sub-ADC 52, the input analog signal V.
, and an amplifier 70.
The second capacitors 64, 66, 68 are arranged in parallel and are capable of sharing the same input and output.
The switches 60 can be realized with typical switching devices such as transistors.
Each switch 60 closes and opens according to the operational phase of the MDAC 50.
That is, switches marked with a 1 in FIG.
5 are exclusively closed during a sample phase, while switches marked with a 2 are exclusively closed during a hold phase.
The first capacitor 62 has a capacitance of C.
sub.
f, and the second capacitors 64, 66, 68 have capacitances of C.
sub.
s,l, C.
sub.
s,i, C.
sub.
s,N respectively.
Although, only three second capacitors 64, 66, 68 are illustrated, the present invention requires simply a minimum of two second capacitors, with a maximum of as many as practical.
The sum of capacitances of all second capacitors 64, 66, 68 used in the MDAC 50 should be selected as nominally equal to the capacitance of the first capacitor 62 such that: C.
sub.
f.
apprxeq.
C.
sub.
s,1 +C.
sub.
s,2, + .
.
.
+C.
sub.
s,N In operation, during the sample phase, the switches 60 are set such that all capacitors 62, 64, 66, 68 are connected to sample the input signal V