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DC power switch with inrush prevention
| Details |
Inventors: Li, Edward; Herrmann, John E.;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Stephan; Steven L.
Assistant Examiner: Sterrett; Jeffrey
Attorney, Agent or Firm: Melamed; Phillip H.
A DC power switch (10) for a capacitive load (11) has a main transistor (Q1) in series with the load between positive and negative DC bus terminals (B.sup.+, B.sup.-). A secondary transistor (Q2) and a resistor (R.sub.1) are connected in series and this series connection is connected in parallel to the main transistor (Q1). A control circuit (20; 50) is connected to the main and secondary transistors (Q1, Q2) and controls them. In response to an enable signal (26), the secondary transistor (Q2) is initially turned on such that it and the resistor provide the initial charging current for the capacitor load (11) and subsequently the secondary transistor is turned off and the main transistor is turned on such that it provides the subsequent current required by the load. This configuration minimizes the power dissipation ratings required for the transistors while balancing this requirement with the relative rapid providing of charging current for the capacitive load. Fault detection circuitry (30-33) makes sure both the main and secondary transistors are off and interrupts the supply of DC power to the load (11) in the event of a detected fault. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG.
1, the circuitry for a DC power switch 10 is illustrated which is used to supply DC power to an effective capacitive load 11 shown dashed in FIG.
1.
The load 11 is shown as comprising a large effective capacitor 12, of the order of 300 microfarads, connected in parallel with an effective 100 microamp constant current source 13.
The parallel connection of the capacitor 12 and constant current source 13 is connected, via a selective on/off switch 14, to an effective resistive type equivalent load 15.
The components 12 through 15 represent the circuit equivalents of the capacitive load 11.
Preferably the load 11 corresponds to a load such as a switching DC power supply that can supply substantial power to a computer or such component.
It is contemplated that after the effective capacitor 12 is charged up, and the switch 14 is closed, the load 11 will typically draw up to a maximum of 30 amps of current.
Thus any series switch for the load 11 should have at least a 30 amp maximum current capability.
In addition, it is desired to shorten, as much as possible, the time that it takes to initially charge up the capacitor 12, and this should occur without requiring extremely complex or costly circuitry for implementing the function of a series semiconductor switch.
This is achieved by the circuit 10.
In FIG.
1, positive and negative DC power bus terminals B.
sup.
+ and B.
sup.
- are provided.
In the preferred embodiment, the voltage between the terminals B.
sup.
+ and B.
sup.
- can vary anywhere from a minimum of 280 volts to a maximum of 430 volts DC.
A main semiconductor switch device Q1, preferably comprising an IGBT (insulated gate bipolar transistor) or a power FET transistor, is connected in series with the capacitive load 11 between the positive and negative DC bus terminals B.
sup.
+ and B.
sup.
-.
The transistor Q1 has a pair of main output electrodes, corresponding to collector and emitter electrodes, with the impedance between these electrodes being determined in accordance with a control signal received at the gate, or main, control electrode of the transistor Q1
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