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Digital to analog converter
| Details |
Inventors: Neidorff, Robert Alan;
Assignee: Unitrode Corporation (Merrimack, NH)
Primary Examiner: Hoff; Marc S.
Assistant Examiner:
Attorney, Agent or Firm: Weingarten, Schurgin, Gagnebin & Hayes LLP
A multi-stage digital to analog converter with increased speed and enhanced accuracy. Multiple resistor ladders are interconnected through switches with the first resistor ladder converting the most significant bits and successive ladders converting lesser significant bits. The resistance values of the resistors of each ladder are greater than those of the preceding ladders in order to minimize inaccuracies due to loading. In one embodiment, the last resistor ladder, processing the least significant bits of the digital word to be converted, is a binary weighted resistor divider. A monolithic fabrication technique includes a common resistor biasing scheme to switch the voltage across parasitic capacitances associated with the resistors in each ladder in common mode, thereby increasing the converter speed. |
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DETAILED DESCRIPTION In accordance with the invention, a monolithic digital to analog (D/A) converter circuit includes multiple stages for converting a digital word into a corresponding analog voltage with increased speed and enhanced accuracy.
Each stage of the converter includes a resistor ladder coupled to a resistor ladder of an adjacent stage through a plurality of switches.
The number of resistors comprising each resistor ladder is related to the number of bits resolved by the particular stage with the first ladder resolving higher order bits and subsequent ladders resolving lower order bits.
More particularly, a first portion of the switches interconnecting adjacent resistor ladders have first terminals coupled to the first resistor ladder and second terminals coupled to a top output node of the first stage and to a top input node of the second stage.
A second portion of the switches likewise have first terminals coupled to the first resistor ladder and second terminals coupled to a bottom output node of the first stage and to a bottom input node of the second stage.
A decoder is provided for receiving a digital word to be converted and controlling the switches in accordance with the bits of the digital word.
The resistors of each stage have resistance values greater than the resistors of the preceding stages in order to prevent disadvantageous loading and thus, to enhance conversion accuracy.
More particularly, the accuracy of the converter is enhanced without requiring the added complexity and inaccuracies associated with the use of buffer amplifiers to isolate adjacent stages.
In one embodiment, the resistors of the first stage are comprised of polycrystalline silicon and the resistors of the subsequent stages are diffusion resistors.
In accordance with a further aspect of the invention, the integrated circuit resistors of each resistor ladder are biased to a common substrate which, in turn, is biased to the top output node of the preceding stage (i.
e.
, to the top input node of the biased stage)
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