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Home Coded Dual-reference-voltage-buffer-and-method-for-updating-CDAC-bit-capacitors

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Details
Inventors: Fees, Andreas O.;
Assignee: Burr-Brown Corporation (Tucson, AZ)
Primary Examiner: Young; Brian
Assistant Examiner: Wamsley; Patrick
Attorney, Agent or Firm: Cahill, Sutton & Thomas P.L.C.

A circuit for producing a stable CDAC reference voltage in a successive approximation analog-to-digital converter includes a circuit (27) producing an input reference voltage (VREFIN), and a buffer circuit (12) producing a stable reference voltage in response to the input reference voltage. The buffer circuit includes an amplifier (13) having a non-inverting input receiving the input reference voltage. A first buffer (13B) receives the output of the amplifier and produces output that is fed back to an inverting input of the amplifier. A second buffer (18) also receives the amplifier output. A first transistor switch (19) couples the output of the second buffer to a CDAC. A second transistor switch (29) couples the CDAC to ground. A third transistor switch (26) couples the first buffer to the CDAC. The first transistor switch (19) closes to cause an initial "coarse" charging of a first capacitance of the CDAC by the second buffer (18). The third transistor switch (26) closes after the coarse charging to perform a final precise "fine" charging of the first capacitance of the CDAC by the first buffer circuit (13B). Coarse and fine discharging of the CDAC to ground also are provided to increase accuracy of the analog-to-digital converter and to minimize RFI produced thereby.

DETAILED DESCRIPTION Accordingly, it is an object of the invention to provide a precision reference voltage circuit that avoids instability caused by a large peak current supplied to a load.
It is another object of the invention to provide a higher conversion rate in a successive approximation analog-to-digital converter utilizing an internal CDAC.
It is another object of the invention to prevent the conversion speed of a successive approximation analog-to-digital converter from being limited by instability in a reference voltage buffer.
It is another object of the invention to reduce RFI caused by large fast current spikes produced during a successive approximation process in a successive approximation analog-to-digital converter.
It is another object of the invention to provide a precision reference voltage circuit that is relatively insensitive to parasitic resistances and inductances during charging of a CDAC array capacitance to a reference voltage (or discharging it to a ground reference voltage).
Briefly described, and in accordance with one embodiment thereof, the invention provides a circuit and method for producing a stable reference voltage, by providing a circuit (27) that produces a reference voltage (VREFIN) on a first conductor (25), a buffer circuit (12) coupled to the first conductor (25) and producing a stable reference voltage on a second conductor (16), the buffer circuit 12 including an amplifier circuit (13) having an inverting input (-), a non-inverting input (+) coupled to the first conductor (25), and an output coupled to a third conductor (11), a first buffer circuit (13B) having an input coupled to the third conductor (11) and an output coupled by a fourth conductor (14) to the inverting input (-), the buffer circuit 12 also including a second buffer circuit (18) having an output (20) coupled to the second conductor (16) and an input coupled to the third conductor (11).
In a described embodiment, the reference voltage is a CDAC reference voltage in a successive approximation analog-to-digital converter



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